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    Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    102.
    发明申请
    Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20210233801A1

    公开(公告)日：2021-07-29

    申请号：US17228937

    申请日：2021-04-13

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  Yongjun Jeff Hu

    IPC: H01L21/762 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.

    Methods Of Forming NAND Cell Units
    103.
    发明申请
    Methods Of Forming NAND Cell Units 有权

    公开(公告)号：US20210210623A1

    公开(公告)日：2021-07-08

    申请号：US17206324

    申请日：2021-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu

    IPC: H01L29/66 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115 ,  H01L27/1157

    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

    Memory arrays and methods used in forming a memory array comprising strings of memory cells
    104.
    发明授权
    Memory arrays and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11011408B2

    公开(公告)日：2021-05-18

    申请号：US16599856

    申请日：2019-10-11

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  Yongjun Jeff Hu

    IPC: H01L21/762 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/3115

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.

    Methods of forming NAND cell units
    105.
    发明授权
    Methods of forming NAND cell units 有权

    公开(公告)号：US10971607B2

    公开(公告)日：2021-04-06

    申请号：US16548003

    申请日：2019-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu

    IPC: H01L29/66 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115 ,  H01L27/1157

    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

    Methods of forming memory cells and memory devices
    106.
    发明授权
    Methods of forming memory cells and memory devices 有权

    公开(公告)号：US10923657B2

    公开(公告)日：2021-02-16

    申请号：US16521046

    申请日：2019-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  Durai Vishak Nirmal Ramaswamy ,  Qian Tao ,  Yongjun Jeff Hu ,  Everett A. McTeer

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.

    Integrated Structures and Methods of Forming Integrated Structures
    108.
    发明申请
    Integrated Structures and Methods of Forming Integrated Structures 审中-公开

    公开(公告)号：US20200083238A1

    公开(公告)日：2020-03-12

    申请号：US16684515

    申请日：2019-11-14

    Applicant: Micron Technology, Inc.

    Inventor： Yongjun Jeff Hu ,  Allen McTeer

    IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/322 ,  H01L21/02

    Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.

    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS
    110.
    发明申请
    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS 审中-公开

    公开(公告)号：US20190355902A1

    公开(公告)日：2019-11-21

    申请号：US16266777

    申请日：2019-02-04

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

    IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

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