公开(公告)号：US09640260B2

公开(公告)日：2017-05-02

申请号：US14320174

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: H01L29/66 ,  G11C16/04 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/792 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

公开(公告)号：US20160372452A1

公开(公告)日：2016-12-22

申请号：US15254586

申请日：2016-09-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

公开(公告)号：US20150170991A1

公开(公告)日：2015-06-18

申请号：US14105940

申请日：2013-12-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jian Li ,  Steven K. Groothuis ,  Michel Koopmans

IPC: H01L23/373 ,  H01L25/065

CPC classification number: H01L21/4882 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16257 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

Abstract translation: 本文公开了具有热隔离件和相关联的系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括限定空腔的导热壳体，腔内的第一半导体管芯的堆叠，以及相对于第一管芯堆叠堆叠并由封装衬底承载的第二半导体管芯。 半导体管芯组件还包括设置在封装衬底和导热壳体之间的热隔离件。 热隔离物可以包括半导体衬底和延伸穿过半导体衬底并且电耦合到第一半导体管芯，第二半导体管芯和封装衬底的堆叠的多个导电通孔。