公开(公告)号：US20080232013A1

公开(公告)日：2008-09-25

申请号：US12134061

申请日：2008-06-05

申请人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

摘要翻译： 用于静电放电（ESD）保护的电路包括电阻器，与电阻器串联连接的电容器，包括栅极的第一晶体管，栅极连接到第一电源，通过电阻向栅极提供第一电压，第一 端子连接到第一电源，第二晶体管包括栅极，栅极连接到第二电源，第二电源提供小于第一电压的第二电压，第二晶体管具有连接到第二电源的第一端子 第一晶体管的端子和包括栅极的第三晶体管，栅极连接到第二电源，第三晶体管的第一端子连接到第二晶体管的第二端子，第二端子连接到第二晶体管， 参考电压不同于第一电压和第二电压。

公开(公告)号：US20080203424A1

公开(公告)日：2008-08-28

申请号：US12118364

申请日：2008-05-09

申请人： Zi-Ping Chen ,  Ming-Dou Ker

发明人： Zi-Ping Chen ,  Ming-Dou Ker

IPC分类号： H01L33/00 ,  H01L23/62

CPC分类号： H01L27/0255

摘要： A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation regions and the buried layer isolate the connection zone and the well from the substrate. The first doped region in the well is a first electrode. The well and the connection region are electrically connected, acting as a second electrode.

摘要翻译： 具有低衬底电流泄漏并适用于BiCMOS工艺技术的二极管。 在半导体衬底上形成掩埋层。 连接区域和阱接触埋层。 隔离区域与埋层的两侧相邻，每一个都比埋层更深。 隔离区域和掩埋层将连接区域和阱与衬底隔离。 阱中的第一掺杂区域是第一电极。 阱和连接区域电连接，用作第二电极。

公开(公告)号：US20080106835A1

公开(公告)日：2008-05-08

申请号：US11842177

申请日：2007-08-21

申请人： Ming-Dou Ker ,  Chih-Kang Deng

发明人： Ming-Dou Ker ,  Chih-Kang Deng

IPC分类号： H02H9/00

CPC分类号： G02F1/136204 ,  H01L27/0248

摘要： An active device array substrate includes pixel units, scan lines, data lines, electrostatic discharge (ESD) protection elements, a short ring and an ESD biased generator. Each pixel unit is electrically connected to the corresponding scan line and data line. Each ESD protection element has a first connection terminal, a second connection terminal and a third connection terminal, wherein the first connection terminal is electrically connected to one of the corresponding scan line and data line, the second connection terminal is electrically connected to the short ring, and the third connection terminal is electrically connected to the ESD biased generator. As an ESD stress occurs, the ESD biased generator provides a voltage to the ESD protection elements to turn on them. It causes that the accumulated electrostatic charges are conducted into the lowest potential of the substrate through the short rings, so as to prevent the pixel units from ESD damaging.

摘要翻译： 有源器件阵列衬底包括像素单元，扫描线，数据线，静电放电（ESD）保护元件，短环和ESD偏置发生器。 每个像素单元电连接到相应的扫描线和数据线。 每个ESD保护元件具有第一连接端子，第二连接端子和第三连接端子，其中第一连接端子电连接到相应的扫描线和数据线之一，第二连接端子电连接到短环 并且第三连接端子电连接到ESD偏置发生器。 当ESD应力发生时，ESD偏置发生器向ESD保护元件提供电压以接通它们。 这导致累积的静电电荷通过短环进入衬底的最低电位，以防止像素单元受到ESD损害。

公开(公告)号：US20070171587A1

公开(公告)日：2007-07-26

申请号：US11307168

申请日：2006-01-26

申请人： Chien-Ming Lee ,  Ming-Dou Ker

发明人： Chien-Ming Lee ,  Ming-Dou Ker

IPC分类号： H02H9/00

CPC分类号： H01L27/0285

摘要： The present invention provides ESD protection circuits. The circuit includes: a resistor, a capacitance, a first transistor, an inverter set, and a second transistor. The resistor is connected between a first voltage and node N1. The capacitor is connected between node N1 and a second voltage. The first transistor has a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, and a third terminal coupled to node N2. The inverter set has an input terminal coupled to node N1 and an output terminal coupled to node N2. The second transistor has a first terminal coupled to a first inverter of the inverter set, a second terminal coupled to the second voltage, and a third terminal coupled to an output terminal of a second inverter of the inverter set. The output terminals of the first and the second inverters correspond to opposite logic levels.

摘要翻译： 本发明提供ESD保护电路。 该电路包括：电阻器，电容器，第一晶体管，反相器组和第二晶体管。 电阻连接在第一电压和节点N 1之间。 电容器连接在节点N1和第二电压之间。 第一晶体管具有耦合到第一电压的第一端子，耦合到第二电压的第二端子和耦合到节点N 2的第三端子。 逆变器组具有耦合到节点N1的输入端和耦合到节点N 2的输出端。 第二晶体管具有耦合到逆变器组的第一反相器的第一端子，耦合到第二电压的第二端子和耦合到逆变器组的第二反相器的输出端子的第三端子。 第一和第二反相器的输出端对应于相反的逻辑电平。

公开(公告)号：US07244992B2

公开(公告)日：2007-07-17

申请号：US10727550

申请日：2003-12-05

申请人： Ming-Dou Ker ,  Che-Hao Chuang

发明人： Ming-Dou Ker ,  Che-Hao Chuang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.

摘要翻译： 一种适用于静电放电（ESD）保护电路的半导体器件，包括半导体衬底，在衬底中形成的第一阱，在衬底中形成的第二阱以及形成在第二阱中的第一掺杂区，其中， 第一阱，第二阱和第一掺杂区域共同形成寄生双极结型晶体管（BJT），其中第一阱是BJT的集电极，第二阱是BJT的基极，第一掺杂区域 是BJT的发射器。

公开(公告)号：US20060256489A1

公开(公告)日：2006-11-16

申请号：US11126134

申请日：2005-05-10

申请人： Ming-Dou Ker ,  Cheng-Ming Lee

发明人： Ming-Dou Ker ,  Cheng-Ming Lee

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H03F1/52 ,  H03F3/195 ,  H03F3/60 ,  H03F2200/441 ,  H03F2200/444 ,  H03F2200/451

摘要： An ESD protection circuit with impedance matching for radio frequency integrated circuits is provided. Nodes at the ends of a transmission line, respectively have at least one ESD component coupled between each and one of the power rails. The ESD components discharge ESD currents and the transmission lines provide RF matching.

摘要翻译： 提供了一种具有射频集成电路阻抗匹配的ESD保护电路。 在传输线的端部处的节点分别具有耦合在每个和一个电源轨道之间的至少一个ESD部件。 ESD元件放电ESD电流，传输线提供RF匹配。

公开(公告)号：US07064942B2

公开(公告)日：2006-06-20

申请号：US10440083

申请日：2003-05-19

申请人： Ming-Dou Ker ,  Wen-Yu Lo

发明人： Ming-Dou Ker ,  Wen-Yu Lo

IPC分类号： H02H9/00

CPC分类号： H01L27/0285 ,  H02H9/046

摘要： An ESD protection circuit with tunable gate-bias coupled between a first and second pads for receiving power supply voltages. The ESD protection circuit includes a diode, a resistor coupled between the cathode of the diode and the first pad, a capacitor coupled between the cathode of the diode and the second pad, a first transistor of a first conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the second pad, a second transistor of a second conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the first pad, and a third transistor of the first conductivity type having a gate coupled to the anode of the diode, a drain coupled to the first pad and a source coupled to the second pad.

摘要翻译： 具有耦合在第一和第二焊盘之间的可调门限偏压的ESD保护电路，用于接收电源电压。 ESD保护电路包括二极管，耦合在二极管的阴极和第一焊盘之间的电阻器，耦合在二极管的阴极和第二焊盘之间的电容器，第一导电类型的第一晶体管，其栅极耦合到 二极管的阴极，耦合到二极管的阳极的漏极和耦合到第二焊盘的源极，具有耦合到二极管的阴极的栅极的第二导电类型的第二晶体管，耦合到二极管的阳极的漏极 二极管和耦合到第一焊盘的源，以及第一导电类型的第三晶体管，其具有耦合到二极管的阳极的栅极，耦合到第一焊盘的漏极和耦合到第二焊盘的源极。

公开(公告)号：US07046036B2

公开(公告)日：2006-05-16

申请号：US10790733

申请日：2004-03-03

申请人： Shih-Lun Chen ,  Ming-Dou Ker

发明人： Shih-Lun Chen ,  Ming-Dou Ker

IPC分类号： H03K19/02

CPC分类号： H03K3/356113 ,  H03K17/102 ,  H03K19/00315

摘要： An output buffer circuit with low-voltage devices to driver high-voltage signals for PCI-X applications is proposed. Because power supply voltage of PCI-X is at 3.3V, the high-voltage gate-oxide stress is a serious problem to design PCI-X I/O circuit in a 0.13 μm 1V/2.5V CMOS process with only low-voltage gate oxide. This proposed output buffer circuit can be operated at 133 MHz in 3.3V PCI-X environment without causing high-voltage gate-oxide reliability problem. In this design, the circuit is implemented in a 0.13 μm 1V/2.5V CMOS process and the output signal swing can be 3.3V. Besides, a level converter that converts 0V˜1V voltage swing to 1V˜3.3V voltage swing is also presented.

摘要翻译： 提出了一种具有低电压器件的驱动器用于PCI-X应用的高电压信号的输出缓冲电路。 由于PCI-X的电源电压为3.3V，高压栅极氧化应力是在0.13 mum 1V / 2.5V CMOS工艺中设计PCI-X I / O电路的严重问题，只有低压栅极 氧化物。 该提出的输出缓冲电路可以在3.3V PCI-X环境中工作在133 MHz，而不会导致高压栅氧化可靠性问题。 在这种设计中，电路采用0.13 mum 1V / 2.5V CMOS工艺，输出信号摆幅可以为3.3V。 此外，还提出了将0V〜1V电压摆幅转换为1V〜3.3V的电压摆幅的电平转换器。

公开(公告)号：US07038276B2

公开(公告)日：2006-05-02

申请号：US10434169

申请日：2003-05-09

申请人： Ming-Dou Ker ,  Wen-Hsia Kung ,  Ya-Hsiang Tai

发明人： Ming-Dou Ker ,  Wen-Hsia Kung ,  Ya-Hsiang Tai

IPC分类号： H01L29/76

CPC分类号： H01L29/78615

摘要： A thin-film transistor (TFT) with body contacts is disclosed. It is used in polysilicon TFT LCD's. A body contact region for separating the gate electrode, a source region, and a drain region is made in the TFT. Through the dopants in the body contact region and different impurities in the source region and the drain region, a body-trigger bias is imposed on the body of the TFT. This method reduces the threshold voltage of the TFT driving circuit, thereby increasing the driving current.

摘要翻译： 公开了一种具有体触点的薄膜晶体管（TFT）。 它用于多晶硅TFT LCD。 在TFT中制造用于分离栅电极，源极区和漏极区的体接触区域。 通过体接触区域中的掺杂剂和源极区域和漏极区域中的不同杂质，对TFT的主体施加体触发偏置。 该方法降低了TFT驱动电路的阈值电压，从而增加了驱动电流。

公开(公告)号：US07009826B2

公开(公告)日：2006-03-07

申请号：US11194021

申请日：2005-07-28

申请人： Ming-Dou Ker ,  Cheng-Ming Lee ,  Tung-Yang Chen

发明人： Ming-Dou Ker ,  Cheng-Ming Lee ,  Tung-Yang Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0288 ,  H01L23/60 ,  H01L24/06 ,  H01L27/0255 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

摘要翻译： 包括单个或多个并联电感器和电容器（也称为LC箱）的ESD保护电路设计，以避免ESD电路中的寄生电容的功率损耗。 所描述的第一个设计包括一个LC液箱结构。 第二个包括两个LC坦克结构。 这些结构可以扩展，形成堆积在n级液晶盒中的ESD保护电路结构。 所描述的最后一个设计是通过堆叠第一设计形成的ESD保护电路。 这些设计可以避免由ESD寄生电容引起的功率增益损失，因为LC槽的参数可以设计成在所需工作频率下谐振。 这些设计中的每一个都可以稍微修改，以创建具有相同ESD保护功能的变体设计。