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    Techniques for Enabling Multiple Vt Devices Using High-K Metal Gate Stacks
    101.
    发明申请
    Techniques for Enabling Multiple Vt Devices Using High-K Metal Gate Stacks 有权
    使用高K金属栅极堆栈启用多个Vt器件的技术

    公开(公告)号：US20100164011A1

    公开(公告)日：2010-07-01

    申请号：US12720354

    申请日：2010-03-09

    Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

    Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

    IPC: H01L29/78

    CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

    Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

    Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

    SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES
    102.
    发明申请
    SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES 有权
    用于具有共同逻辑设备的后盖控制SRAM的基板解决方案

    公开(公告)号：US20080258221A1

    公开(公告)日：2008-10-23

    申请号：US12144272

    申请日：2008-06-23

    Applicant: Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    Inventor： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    IPC: H01L27/11

    CPC classification number: H01L27/1108

    Abstract: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

    Abstract translation: 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

    Method for passivation of plasma etch defects in DRAM devices
    103.
    发明授权
    Method for passivation of plasma etch defects in DRAM devices 失效

    公开(公告)号：US07407871B2

    公开(公告)日：2008-08-05

    申请号：US11515534

    申请日：2006-09-05

    Applicant: Arvind Kumar ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Subramanian Krishnan

    Inventor： Arvind Kumar ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Subramanian Krishnan

    IPC: H01L21/322

    CPC classification number: H01L21/26513 ,  H01L27/10873

    Abstract: A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena. However to insure the group V implanted species remain at or near the semiconductor surface for optimum defect passivation, the group V element implantation procedure is performed after all high temperature DRAM fabrication steps, such as selective oxidation for creation of oxide spacers on the sides of the conductive gate electrode, have been completed. A slow diffusing implanted arsenic ion is the optimum candidate for passivation while faster diffusing group V elements such as phosphorous are not as attractive for defect passivation.

    Method for passivation of plasma etch defects in DRAM devices
    104.
    发明申请
    Method for passivation of plasma etch defects in DRAM devices 失效
    DRAM器件中等离子体蚀刻缺陷钝化的方法

    公开(公告)号：US20080124814A1

    公开(公告)日：2008-05-29

    申请号：US11515534

    申请日：2006-09-05

    Applicant: Arvind Kumar ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Subramanian Krishnan

    Inventor： Arvind Kumar ,  Keen Wah Chow ,  Devesh Kumar Datta ,  Subramanian Krishnan

    IPC: H01L21/02

    CPC classification number: H01L21/26513 ,  H01L27/10873

    Abstract: A process for fabricating an MOS device specifically a DRAM device, featuring passivation of defects in regions of a semiconductor substrate wherein defects left unpassivated can deleteriously influence data retention time, has been developed. A high density plasma dry etching procedure used to define the DRAM conductive gate electrode can create unwanted defects in a region near the surface of uncovered portions of the semiconductor substrate during the high density plasma procedure over etch cycle. Implantation of a group V element such as arsenic can be used to passivate the unwanted plasma etch defects, thus reducing the risk of defect related device leakage phenomena. However to insure the group V implanted species remain at or near the semiconductor surface for optimum defect passivation, the group V element implantation procedure is performed after all high temperature DRAM fabrication steps, such as selective oxidation for creation of oxide spacers on the sides of the conductive gate electrode, have been completed. A slow diffusing implanted arsenic ion is the optimum candidate for passivation while faster diffusing group V elements such as phosphorous are not as attractive for defect passivation.

    Abstract translation: 已经开发了制造具有DRAM器件的MOS器件的工艺，其特征在于半导体衬底的区域中的缺陷钝化，其中缺陷未被激活可以有害地影响数据保留时间。 用于限定DRAM导电栅电极的高密度等离子体干蚀刻方法可以在蚀刻周期的高密度等离子体工艺期间在半导体衬底的未覆盖部分的表面附近的区域中产生不想要的缺陷。 可以使用诸如砷的V族元素的植入来钝化不需要的等离子体蚀刻缺陷，从而降低与缺陷相关的器件泄漏现象的风险。 然而，为了确保V族植入物质保留在半导体表面处或附近，以获得最佳缺陷钝化，在所有高温DRAM制造步骤之后执行V族元素注入程序，例如用于在 导电栅电极，已经完成。 缓慢扩散的注入砷离子是钝化的最佳候选物，而较快扩散V族元素（如磷）对缺陷钝化不具有吸引力。

    Management of links to data embedded in blocks of data
    109.
    发明授权
    Management of links to data embedded in blocks of data 有权
    管理数据嵌入数据的链接

    公开(公告)号：US06954934B2

    公开(公告)日：2005-10-11

    申请号：US09811060

    申请日：2001-03-15

    Applicant: Arvind Kumar

    Inventor： Arvind Kumar

    IPC: G06F9/00 ,  G06F9/54 ,  G06F15/163 ,  G06F17/30

    CPC classification number: G06F17/30882

    Abstract: Management of links, such as URLs or other link formats, that have been embedded within blocks of data, such as data received by an E-mail application program, file transfer program, or other data transfer environment. When a block of data is received, an agent or other construct examines the block of data to identify links within the block of data. Meta-data associated with the link is extracted, and the link and associated meta-data is stored in a collective. The collective may be displayed and organized with a viewer. The viewer may be integral to an application program, such as an E-mail application program, or it may integral to an operating system, or it may be a standalone application program.

    Abstract translation: 已经嵌入在数据块内的诸如URL或其他链接格式的链接的管理，例如由电子邮件应用程序接收的数据，文件传输程序或其他数据传输环境。 当接收到数据块时，代理或其他结构检查数据块以识别数据块内的链路。 提取与链接相关联的元数据，并将链接和相关联的元数据存储在集合中。 集体可以用观众显示和组织。 观众可能是应用程序（例如电子邮件应用程序）的组成部分，或者它可能与操作系统集成，或者它可以是独立的应用程序。

    Radiation therapy system using interior-point methods and convex models for intensity modulated fluence map optimization
    110.
    发明申请
    Radiation therapy system using interior-point methods and convex models for intensity modulated fluence map optimization 审中-公开
    使用内点法和凸模型进行强度调制注量地图优化的放射治疗系统

    公开(公告)号：US20050207531A1

    公开(公告)日：2005-09-22

    申请号：US11039331

    申请日：2005-01-20

    Applicant: James Dempsey ,  Ravindra Ahuja ,  Arvind Kumar ,  Jonathan Li ,  H. Romeijn

    Inventor： James Dempsey ,  Ravindra Ahuja ,  Arvind Kumar ,  Jonathan Li ,  H. Romeijn

    IPC: A61N5/10

    CPC classification number: A61N5/1031 ,  A61N5/1042

    Abstract: A method of determining a treatment plan for intensity modulated radiation treatment (IMRT) divides a three-dimensional volume of a patient into a grid of dose voxels. At least a portion of the dose voxels are designated to belong to at least one target or to at least one critical structure. An ionizing radiation dose as delivered by a plurality of beamlets each having a beamlet intensity is modeled. A non-linear convex voxel-based penalty function model is provided for optimizing a fluence map. The fluence map defines the beamlet intensities for each of the plurality of beamlets. The model is then solved based on defined clinical criteria for the target and the critical structure using an interior point algorithm with dense column handling to obtain a globally optimal fluence map.

    Abstract translation: 确定强度调制辐射治疗（IMRT）的治疗计划的方法将患者的三维体积分成剂量体素的网格。 剂量体素的至少一部分被指定为属于至少一个靶或至少一个关键结构。 由多个具有子束强度的子束传送的电离辐射剂量被建模。 提供了一种非线性凸基于体素的惩罚函数模型，用于优化注量图。 注量图定义了多个子束中的每一个的子束强度。 然后使用具有密集列处理的内点算法，基于目标和临界结构的定义临床标准来解决该模型，以获得全局最优注量图。

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