公开(公告)号：US20240170463A1

公开(公告)日：2024-05-23

申请号：US18511547

申请日：2023-11-16

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA

IPC: H01L25/10 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L23/5227 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48137

Abstract: A second distance between a second lower inductor and a second upper inductor, which are components of a second transformer is smaller than a first distance between a first lower inductor and a first upper inductor which are components of a first transformer.

公开(公告)号：US20240145553A1

公开(公告)日：2024-05-02

申请号：US18051935

申请日：2022-11-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/7816

Abstract: LDMOS having an n-type source region and a drain region formed on an upper surface of a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate dielectric film, and a field plate electrode formed on the semiconductor substrate between the gate electrode and the drain region via a dielectric film having a larger film thickness than the gate dielectric film, is formed. Here, the field plate electrode has a larger work function than an n-type semiconductor region formed in the semiconductor substrate directly below the field plate electrode.

公开(公告)号：US20240105761A1

公开(公告)日：2024-03-28

申请号：US18358381

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA

IPC: H10N69/00 ,  H01F17/00 ,  H01F27/28 ,  H01L23/522 ,  H01L23/64 ,  H04B5/02

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F27/2828 ,  H01L23/5227 ,  H01L23/645 ,  H04B5/02 ,  H01F2017/0073 ,  H01F2017/0086

Abstract: A semiconductor chip includes a transformer that performs contactless communication between different potentials. The semiconductor chip includes a semiconductor substrate, a semiconductor region formed in an upper surface of the semiconductor substrate, and the transformer formed over the semiconductor substrate. Here, the transformer includes a lower inductor, a lead wiring portion electrically connected to the lower inductor, and an upper inductor 100 magnetically coupled to the lower inductor, and the lead wiring portion has a wiring facing the semiconductor region.

公开(公告)号：US20230369253A1

公开(公告)日：2023-11-16

申请号：US18181274

申请日：2023-03-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi MIYAKI

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a redistribution layer. The first semiconductor chip and the second semiconductor chip are arranged spaced apart from each other in a second direction orthogonal to a first direction. The redistribution layer is disposed across over the first semiconductor chip and the second semiconductor chip. The redistribution layer includes a first inductor and a second inductor. The first inductor and the second inductor are spaced apart and face each other in a third direction orthogonal to the first direction and the second direction. The first inductor and the second inductor are electrically connected to the first semiconductor chip and the second semiconductor chip, respectively. The first inductor and the second inductor are wound across over the first semiconductor chip and the second semiconductor chip in a plane orthogonal to the third direction.

公开(公告)号：US20230231042A1

公开(公告)日：2023-07-20

申请号：US18055635

申请日：2022-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0657 ,  H01L29/861 ,  H01L29/66348

Abstract: A reliability of a semiconductor device is ensured, and performance of the device is improved. A semiconductor device including a region 1A and a region 2A includes an n-type semiconductor substrate TS having a front surface BS1, BS2 and a back surface SUB, a IGBT formed on a semiconductor substrate in a region 1A, and a diode formed on the semiconductor substrate SUB in a region 2A. And a thickness T1 of the semiconductor substrate SUB in the region 1A is smaller than a thickness of the semiconductor substrate T2 in the region 2A.

公开(公告)号：US20230065171A1

公开(公告)日：2023-03-02

申请号：US17887184

申请日：2022-08-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi MIYAKI

IPC: H05K1/14 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: A semiconductor device includes a first semiconductor chip in which a first multilayer wiring structure including a first coil and a second coil is formed and a second semiconductor chip in which a second multilayer wiring structure including a third coil and a fourth coil is formed. The second semiconductor chip is joined to the first semiconductor chip such that the first coil (second coil) and the third coil (fourth coil) are overlapped and the second semiconductor chip does not have an offset structure with respect to the first semiconductor chip. The second semiconductor chip is joined to the first semiconductor chip such that it is not overlapped with a pad for the first semiconductor chip and a pad for the second semiconductor chip.

公开(公告)号：US20230057216A1

公开(公告)日：2023-02-23

申请号：US17876085

申请日：2022-07-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66

Abstract: A semiconductor device and a method of manufacturing the semiconductor device to achieve both of a high breakdown voltage and a low on resistance are provided. A semiconductor substrate includes a convex portion protruding upward from a surface of the semiconductor substrate. An n-type drift region is arranged on the semiconductor substrate so as to be positioned between a gate electrode and an n+-type drain region in plan view, and has an impurity concentration lower than an impurity concentration of the n+-type drain region. A p-type resurf region is arranged in the convex portion and forms a pn junction with the n-type drift region.

公开(公告)号：US20230029438A1

公开(公告)日：2023-01-26

申请号：US17828349

申请日：2022-05-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Masami SAWADA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: Reliability of a semiconductor device is improved by suppressing occurrence of variation in characteristics of the semiconductor device provided with a power MOSFET that has a super junction structure. A fixed charge layer FC is formed in a trench T2 that is formed in an upper surface of a semiconductor substrate SB and is adjacent to a p type body region BD and an n type drift layer DL. The fixed charge layer FC constituting a p column accumulates holes in the semiconductor substrate SB located at a side surface of the trench T2 to form a hole accumulation region HC.

公开(公告)号：US20220238651A1

公开(公告)日：2022-07-28

申请号：US17553251

申请日：2021-12-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Akihiro SHIMOMURA ,  Masami SAWADA

IPC: H01L29/08 ,  H01L29/78 ,  H01L23/495 ,  H01L23/00

Abstract: The semiconductor device according to one embodiment includes a semiconductor substrate having a first surface and a second surface on an opposite side of the first surface, a gate insulating film formed on the first surface, a gate formed on the first surface via the gate insulating film, a source region formed in the first surface side of the semiconductor substrate, a body region formed so as to be in contact with the source region and including a channel region, a drain region formed in the second surface side of the semiconductor substrate, and a drift region formed so as to be in contact with the second surface side of the body region and the first surface side of the drain region. The semiconductor substrate has at least one concave portion formed in the second surface and being recessed toward the first surface.

公开(公告)号：US20220020668A1

公开(公告)日：2022-01-20

申请号：US16928872

申请日：2020-07-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA

IPC: H01L23/485 ,  H01L29/872

Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.