公开(公告)号：US20060039187A1

公开(公告)日：2006-02-23

申请号：US10923651

申请日：2004-08-20

Applicant: Daniel Braun ,  Richard Ferrant

Inventor： Daniel Braun ,  Richard Ferrant

IPC: G11C11/00

CPC classification number: H01L27/224 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1655 ,  G11C11/1659 ,  H01L27/228

Abstract: A magnetic memory element comprising a magnetic storage element having at least one magnetic layer made of a magnetic material and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, the magnetic layer having a magnetic anisotropy with its magnetization vector being magnetically coupled to at least one current line, and a magnetic sensor element for sensing the magnetization of the at least one magnetic layer of the magnetic storage element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to the magnetization vector of the at least one magnetic layer of the magnetic storage element, the magnetic sensor element being conductively coupled to the at least one current line.

Abstract translation: 一种磁存储元件，包括磁存储元件，所述磁存储元件具有至少一个由磁性材料制成的磁性层，并且相对于其上形成有磁存储元件的晶片表面垂直取向，所述磁性层具有磁各向异性，其磁化矢量为 磁耦合到至少一个电流线，以及用于感测磁存储元件的至少一个磁性层的磁化的磁传感器元件，包括至少一个磁性层，该磁性层具有磁耦合到在线的磁化矢量的磁化矢量 所述磁存储元件的至少一个磁性层，所述磁传感器元件导电地耦合到所述至少一个电流线。

公开(公告)号：US20050157580A1

公开(公告)日：2005-07-21

申请号：US11079590

申请日：2005-03-14

Applicant: Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

Inventor： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC: G11C20060101 ,  G11C8/00 ,  G11C11/00 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4097

CPC classification number: G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

Abstract translation: 这里描述和说明了许多发明。 在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。 在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。 本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。 在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列为矩阵排列的多个半导体动态随机存取存储器单元。 每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极 身体区域。 每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。 此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

公开(公告)号：US20050032277A1

公开(公告)日：2005-02-10

申请号：US10937424

申请日：2004-09-07

Applicant: Richard Ferrant ,  T. C. Chan

Inventor： Richard Ferrant ,  T. C. Chan

IPC: H01L27/11 ,  G11C11/412 ,  H01L21/8244 ,  H01L29/76 ,  H01L21/82

CPC classification number: G11C11/412

Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair. The threshold voltage of the first and second pass gate transistors is such that a subthreshold current is provided to the first and second pull-down transistors when the memory cell is not being accessed such that the conduction terminal of the pull-down transistor that is turned off is maintained at a voltage level corresponding to a logic high voltage. In this way, the memory cell is capable of performing a latching function without pull-up transistors.

Abstract translation: 公开了一种随机存取存储单元及其制造方法。 随机存取存储单元包括交叉耦合的第一和第二下拉晶体管，使得第一下拉晶体管的控制端子连接到第二下拉晶体管的导通端子，并且控制端子 第二下拉晶体管连接到第一下拉晶体管的导通端子。 第一栅极晶体管耦合在第一晶体管的导通端和位线对的第一位线之间，第二栅极晶体管耦合在第二晶体管的导通端和位的第二位线之间 线对。 第一和第二栅极晶体管的阈值电压使得当存储单元未被访问时，向第一和第二下拉晶体管提供亚阈值电流，使得转换的下拉晶体管的导通端 关闭保持在对应于逻辑高电压的电压电平。 以这种方式，存储单元能够执行没有上拉晶体管的锁存功能。

公开(公告)号：US06421799B1

公开(公告)日：2002-07-16

申请号：US09364704

申请日：1999-07-30

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C2900

CPC classification number: G11C29/88 ,  G06F11/1008

Abstract: A ROM including an array, each cell of which is accessible by means of a column address and of a row address, includes a parity memory for storing the expected parity of each row and of each column, an electrically programmable one-time programmable address memory, a testing circuit for, during a test phase, calculating the parity of each row and of each column, comparing the calculated and expected parities for each row and each column, and in case they are not equal, marking the row or column in the address memory, and a correction circuit for, in normal mode, inverting the value read from the array cell, having its row and column marked in the address memory.

Abstract translation: 包括阵列的ROM，其每个单元通过列地址和行地址可访问，包括用于存储每行和每列预期奇偶校验的奇偶校验存储器，电可编程一次可编程地址存储器 测试电路，用于在测试阶段期间计算每行和每列的奇偶校验，比较每行和每列的计算和预期奇偶校验，并且在不相等的情况下，将行或列标记在 地址存储器和校正电路，用于在正常模式下将从阵列单元读取的值反转，其中其行和列被标记在地址存储器中。

公开(公告)号：US06360294B1

公开(公告)日：2002-03-19

申请号：US09231423

申请日：1999-01-14

Applicant: Richard Ferrant ,  Michel Bouche

Inventor： Richard Ferrant ,  Michel Bouche

IPC: G06F2100

CPC classification number: G11C11/406 ,  G11C7/06 ,  G11C7/065

Abstract: A device for reading/rewriting a memory cell of a dynamic random-access memory organized in rows and columns, comprises, for each column, a first read/rewrite amplifier, and at least one second read/rewrite amplifier arranged in parallel with the first amplifier. A controller is provided for one of the amplifiers so that the amplifier is able to store the information contained in the memory cell for refreshing thereof, and so that the other amplifier is able to simultaneously perform read/rewrite accesses to and from the memory cell. One of the amplifiers may be permanently dedicated to operations for refreshing the memory cells and the other may be dedicated to read/write operations. Outputs of the amplifiers are connected to common output columns, and the controller includes an interrupter for the output of each amplifier to isolate the output from the corresponding output column and from the corresponding output of the other amplifier.

Abstract translation: 用于读取/重写以行和列组织的动态随机存取存储器的存储单元的装置包括：对于每列，第一读/重写放大器和至少一个第二读/重写放大器与第一 放大器 为放大器中的一个提供控制器，使得放大器能够存储包含在存储器单元中的信息以便其刷新，并且使得另一个放大器能够同时执行对存储器单元的读取/重写访问。 放大器中的一个可以永久专用于刷新存储器单元的操作，另一个可专用于读/写操作。 放大器的输出连接到公共输出列，并且控制器包括用于每个放大器的输出的中断器，以将输出与相应的输出列和另一个放大器的相应输出隔离。

公开(公告)号：US06205077B1

公开(公告)日：2001-03-20

申请号：US09575716

申请日：2000-07-28

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C700

CPC classification number: H03K19/0027 ,  G11C17/18 ,  H03K19/018521

Abstract: A one-time programmable cell including an inverter providing a logic state according to the state of the cell; a fuse coupled between a first supply voltage and the inverter input; and a current source coupled between the fuse and a second supply voltage. The inverter is supplied from the second supply voltage through a first diode-connected transistor and the current source is formed of a second transistor controlled by the inverter output, this second transistor having a threshold voltage greater than that of the first transistor.

Abstract translation: 一次性可编程单元，包括根据单元的状态提供逻辑状态的反相器; 连接在第一电源电压和反相器输入之间的熔丝; 以及耦合在所述熔丝和第二电源电压之间的电流源。 逆变器由第二电源电压通过第一二极管连接的晶体管提供，电流源由逆变器输出控制的第二晶体管形成，该第二晶体管的阈值电压大于第一晶体管的阈值电压。

公开(公告)号：US6091650A

公开(公告)日：2000-07-18

申请号：US321023

申请日：1999-05-27

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G06F11/20 ,  G11C7/00

CPC classification number: G11C29/846 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402 ,  G11C2229/723

Abstract: A memory device includes a defect memory, a test circuit, and a spare memory. The defect memory and the spare memory have as many rows as the array, and each row of the defect memory and the spare memory are selected when the corresponding row of the array is selected. A test circuit locates defective cells of the array and writes addresses in the defect memory to indicate locations of the defective cells. Additionally, a control circuit selects a row of the array based on a selected row address and redirects access to the corresponding row of the spare memory whenever a selected column address corresponds to one of the addresses stored in the defect memory. In one preferred embodiment, each of the rows of the defect memory stores information indicating if there is a defective cell in the corresponding row of the array and the column address of the defective cell. A computer system including such a memory device is also provided.

Abstract translation: 存储器件包括缺陷存储器，测试电路和备用存储器。 缺陷存储器和备用存储器具有与阵列一样多的行，并且当选择阵列的相应行时，选择缺陷存储器和备用存储器的每一行。 测试电路定位阵列的故障单元，并将缺陷存储器中的地址写入以指示故障单元的位置。 另外，只要选择的列地址对应于存储在缺陷存储器中的一个地址，控制电路就基于所选择的行地址选择一行阵列，并重定向到备用存储器的相应行的访问。 在一个优选实施例中，缺陷存储器的每行都存储指示阵列的相应行中是否存在缺陷单元的信息以及有缺陷单元的列地址。 还提供了包括这种存储装置的计算机系统。

公开(公告)号：US5982679A

公开(公告)日：1999-11-09

申请号：US86625

申请日：1998-05-29

Applicant: Richard Ferrant

Inventor： Richard Ferrant

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/848

Abstract: The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

Abstract translation: 本发明涉及一种集成电路，其包括至少一个相同元件的矩阵网络，能够至少在第一方向上被单独地寻址，并且至少包括至少对于该第一方向至少一个冗余元件，以及可逆地抑制 故障元件的操作并通过使用冗余元件来维持电路操作。

公开(公告)号：US5570313A

公开(公告)日：1996-10-29

申请号：US544009

申请日：1995-10-17

Applicant: Thierry Masson ,  Richard Ferrant

Inventor： Thierry Masson ,  Richard Ferrant

IPC: G11C5/00 ,  G11C7/04 ,  G11C11/34 ,  G11C7/02

CPC classification number: G11C5/005

Abstract: The invention concerns a memory cell insensitive to disturbances. The memory cell, that contains information in the form of two complementary logical levels (X, C(X)), each logical level being stored in a node of the cell (N1, N2), is characterized in that it comprises means of storing the same logical level in two different nodes (N1, N2, N3, N4), the said means being able to restore any logical level to its initial state preceding a modification made on it due to a disturbance, as a result of holding the value of one of the two logical levels complementary to the logical level that was modified.

Abstract translation: 本发明涉及对干扰不敏感的记忆体。 存储单元包含两个互补逻辑电平（X，C（X））形式的信息，每个逻辑电平存储在单元（N1，N2）的一个节点中，其特征在于它包括存储 在两个不同节点（N1，N2，N3，N4）中具有相同的逻辑电平，所述装置能够在由于干扰而在其上进行的修改之前将任何逻辑电平恢复到其初始状态，作为保持该值 与修改的逻辑级别互补的两个逻辑级别之一。