公开(公告)号：US07212432B2

公开(公告)日：2007-05-01

申请号：US10955837

申请日：2004-09-30

申请人： Richard Ferrant ,  Daniel Braun

发明人： Richard Ferrant ,  Daniel Braun

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  G11C8/14 ,  G11C11/15 ,  G11C2213/79 ,  H01L29/785

摘要： A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access memory device comprising a plurality of first current lines; a plurality of second current lines; a plurality of third current lines being formed as split current lines; and an array of resistive memory cells arranged in columns defined by said first current lines and rows defined by said third current lines, each resistive memory cell including a resistive memory element and an access transistor connected in series, each memory cell being connected between one of said first current lines and a reference potential, wherein said access transistors being FinFET-type field effect transistors, each one having two independent gates and a common floating body, and wherein each third current line being connected to one of said two independent gates of each one of the access transistors of a row of said array and being connected to one of said two independent gates of each one of the access transistors of an adjacent row of said array. It also relates to a method for its fabrication.

摘要翻译： 一种电阻式存储单元随机存取存储器件及其制造方法。 在一个实施例中，本发明涉及包括多条第一电流线的电阻式存储单元随机存取存储器件; 多条第二电流线; 多条第三电流线被形成为分流电流线; 以及由所述第一电流线限定的列和由所述第三电流线限定的行的电阻性存储单元的阵列，每个电阻性存储单元包括电阻性存储元件和串联连接的存取晶体管，每个存储单元连接在 所述第一电流线和参考电位，其中所述存取晶体管是FinFET型场效应晶体管，每个具有两个独立的栅极和共同的浮动体，并且其中每个第三电流线连接到每个的所述两个独立栅极之一 所述阵列的行的存取晶体管之一并且连接到所述阵列的相邻行的每个存取晶体管的每一个的所述两个独立栅极之一。 它还涉及其制造方法。

公开(公告)号：US07200032B2

公开(公告)日：2007-04-03

申请号：US10923651

申请日：2004-08-20

申请人： Daniel Braun ,  Richard Ferrant

发明人： Daniel Braun ,  Richard Ferrant

IPC分类号： G11C11/00

CPC分类号： H01L27/224 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1655 ,  G11C11/1659 ,  H01L27/228

摘要： A magnetic memory element comprising a magnetic storage element having at least one magnetic layer made of a magnetic material and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, the magnetic layer having a magnetic anisotropy with its magnetization vector being magnetically coupled to at least one current line, and a magnetic sensor element for sensing the magnetization of the at least one magnetic layer of the magnetic storage element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to the magnetization vector of the at least one magnetic layer of the magnetic storage element, the magnetic sensor element being conductively coupled to the at least one current line.

摘要翻译： 一种磁存储元件，包括磁存储元件，所述磁存储元件具有至少一个由磁性材料制成的磁性层，并且相对于其上形成有磁存储元件的晶片表面垂直取向，所述磁性层具有磁各向异性，其磁化矢量为 磁耦合到至少一个电流线，以及磁传感器元件，用于感测磁存储元件的至少一个磁性层的磁化，包括至少一个磁性层，磁化矢量磁耦合到磁场的磁化矢量 所述磁存储元件的至少一个磁性层，所述磁传感器元件导电地耦合到所述至少一个电流线。

公开(公告)号：US20060024886A1

公开(公告)日：2006-02-02

申请号：US10903722

申请日：2004-07-30

申请人： Richard Ferrant ,  Daniel Braun ,  Pascal Louis

发明人： Richard Ferrant ,  Daniel Braun ,  Pascal Louis

IPC分类号： H01L21/336

CPC分类号： H01L27/224

摘要： A MRAM storage device comprises a substrate, on/above of which a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a plurality of isolation diodes are provided. Each memory cell forms a resistive cross point of one word line and one bit line, respectively. Each memory cell is connected to one isolation diode such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell, respectively. The substrate, at least a part of the word lines or at least a part of the bit lines, and the isolation diodes are realized as one common monocrystal semiconductor block.

摘要翻译： MRAM存储设备包括其上/其上提供有多个字线，多个位线，多个存储器单元和多个隔离二极管的衬底。 每个存储单元分别形成一个字线和一个位线的电阻交叉点。 每个存储单元连接到一个隔离二极管，使得单向导电路径分别通过对应的存储单元从字线形成到位线。 基板，字线的至少一部分或位线的至少一部分以及隔离二极管被实现为一个常见的单晶半导体块。

公开(公告)号：US07180160B2

公开(公告)日：2007-02-20

申请号：US10903722

申请日：2004-07-30

申请人： Richard Ferrant ,  Daniel Braun ,  Pascal Louis

发明人： Richard Ferrant ,  Daniel Braun ,  Pascal Louis

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/224

摘要： A MRAM storage device comprises a substrate, on/above of which a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a plurality of isolation diodes are provided. Each memory cell forms a resistive cross point of one word line and one bit line, respectively. Each memory cell is connected to one isolation diode such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell, respectively. The substrate, at least a part of the word lines or at least a part of the bit lines, and the isolation diodes are realized as one common monocrystal semiconductor block.

摘要翻译： MRAM存储设备包括其上/其上提供有多个字线，多个位线，多个存储器单元和多个隔离二极管的衬底。 每个存储单元分别形成一个字线和一个位线的电阻交叉点。 每个存储单元连接到一个隔离二极管，使得单向导电路径分别通过对应的存储单元从字线形成到位线。 基板，字线的至少一部分或位线的至少一部分以及隔离二极管被实现为一个常见的单晶半导体块。

公开(公告)号：US20060067112A1

公开(公告)日：2006-03-30

申请号：US10955837

申请日：2004-09-30

申请人： Richard Ferrant ,  Daniel Braun

发明人： Richard Ferrant ,  Daniel Braun

IPC分类号： G11C11/14 ,  G11C5/06

CPC分类号： H01L27/228 ,  G11C8/14 ,  G11C11/15 ,  G11C2213/79 ,  H01L29/785

摘要： A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access memory device comprising a plurality of first current lines; a plurality of second current lines; a plurality of third current lines being formed as split current lines; and an array of resistive memory cells arranged in columns defined by said first current lines and rows defined by said third current lines, each resistive memory cell including a resistive memory element and an access transistor connected in series, each memory cell being connected between one of said first current lines and a reference potential, wherein said access transistors being FinFET-type field effect transistors, each one having two independent gates and a common floating body, and wherein each third current line being connected to one of said two independent gates of each one of the access transistors of a row of said array and being connected to one of said two independent gates of each one of the access transistors of an adjacent row of said array. It also relates to a method for its fabrication.

摘要翻译： 一种电阻式存储单元随机存取存储器件及其制造方法。 在一个实施例中，本发明涉及包括多条第一电流线的电阻式存储单元随机存取存储器件; 多条第二电流线; 多条第三电流线被形成为分流电流线; 以及由所述第一电流线限定的列和由所述第三电流线限定的行的电阻性存储单元的阵列，每个电阻性存储单元包括电阻性存储元件和串联连接的存取晶体管，每个存储单元连接在 所述第一电流线和参考电位，其中所述存取晶体管是FinFET型场效应晶体管，每个具有两个独立的栅极和共同的浮动体，并且其中每个第三电流线连接到每个的所述两个独立栅极之一 所述阵列的行的存取晶体管之一并且连接到所述阵列的相邻行的每个存取晶体管的每一个的所述两个独立栅极之一。 它还涉及其制造方法。

公开(公告)号：US20060039187A1

公开(公告)日：2006-02-23

申请号：US10923651

申请日：2004-08-20

申请人： Daniel Braun ,  Richard Ferrant

发明人： Daniel Braun ,  Richard Ferrant

IPC分类号： G11C11/00

CPC分类号： H01L27/224 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1655 ,  G11C11/1659 ,  H01L27/228

摘要： A magnetic memory element comprising a magnetic storage element having at least one magnetic layer made of a magnetic material and being vertically oriented relative to a wafer surface on which the magnetic memory element is formed, the magnetic layer having a magnetic anisotropy with its magnetization vector being magnetically coupled to at least one current line, and a magnetic sensor element for sensing the magnetization of the at least one magnetic layer of the magnetic storage element comprising at least one magnetic layer having a magnetization vector being magnetically coupled to the magnetization vector of the at least one magnetic layer of the magnetic storage element, the magnetic sensor element being conductively coupled to the at least one current line.

摘要翻译： 一种磁存储元件，包括磁存储元件，所述磁存储元件具有至少一个由磁性材料制成的磁性层，并且相对于其上形成有磁存储元件的晶片表面垂直取向，所述磁性层具有磁各向异性，其磁化矢量为 磁耦合到至少一个电流线，以及用于感测磁存储元件的至少一个磁性层的磁化的磁传感器元件，包括至少一个磁性层，该磁性层具有磁耦合到在线的磁化矢量的磁化矢量 所述磁存储元件的至少一个磁性层，所述磁传感器元件导电地耦合到所述至少一个电流线。

公开(公告)号：US08575697B2

公开(公告)日：2013-11-05

申请号：US13039167

申请日：2011-03-02

申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC分类号： H01L27/11 ,  H01L27/12 ,  G11C5/06 ,  G11C11/00

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1203

摘要： An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

摘要翻译： 一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。 每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到 第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。 第一和第二电位可以根据电池控制操作的类型进行调制。

公开(公告)号：US08432216B2

公开(公告)日：2013-04-30

申请号：US13007483

申请日：2011-01-14

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G05F1/10 ,  H01L27/105 ,  G06F17/50

CPC分类号： H01L27/1203 ,  H01L29/78609 ,  H01L29/78648

摘要： The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.

摘要翻译： 本发明提供一种特别适用于其环境的数据通道单元，用于在绝缘体上半导体（SeOI）衬底上制造的集成电路中。 数据通道单元包括场效应晶体管阵列，每个晶体管具有形成在SeOI衬底的薄半导体层中的源极区，漏极区和沟道区，并且还具有形成在栅极上的前栅极控制区 渠道区域。 特别地，数据通道单元的一个或多个晶体管还包括形成在沟道区下面的体衬底中的背栅极控制区域，并且被配置为根据其偏置状态来修改晶体管的性能特性。 而且，包括一个或多个数据路径单元的集成电路以及用于设计或驱动这些数据路径单元的方法。

公开(公告)号：US08310866B2

公开(公告)日：2012-11-13

申请号：US12168671

申请日：2008-07-07

申请人： Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

发明人： Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

IPC分类号： G11C11/02 ,  G11C7/00 ,  H01L21/00

CPC分类号： G11C7/04 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/307 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.

摘要翻译： 提出了一种在写入模式工作温度下可编程的热辅助MRAM结构，其包括反铁磁体，人造抗铁磁体，阻挡层和自由磁性层。 抗铁磁体由具有比磁性随机存取存储器结构的写入模式工作温度低的阻挡温度Tb的材料构成。 人造抗铁磁体磁耦合到抗铁磁体，并且包括第一和第二磁性层以及插入其间的耦合层，第一和第二磁性层具有不同的居里点温度。 阻挡层被定位在第二磁性层和自由磁性层之间。

公开(公告)号：US08305803B2

公开(公告)日：2012-11-06

申请号：US12942754

申请日：2010-11-09

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G11C11/40 ,  G11C11/402

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/0711 ,  H01L27/10802 ,  H01L29/086 ,  H01L29/7302

摘要： The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.

摘要翻译： 本发明涉及具有源极，漏极和源极和漏极之间的浮体的FET晶体管的存储单元，以及可以被控制以将电荷注入到FET晶体管的浮动体中的注入器。 注射器包括具有由FET晶体管的主体形成的发射极，基极和集电极的双极晶体管。 具体地说，在存储单元中，双极型晶体管的发射极配置成使FET晶体管的源极作为双极晶体管的基极。 本发明还包括包括根据本发明的第一方面的多个存储器单元的存储器阵列以及控制这种存储器单元的方法。