公开(公告)号：US09214429B2

公开(公告)日：2015-12-15

申请号：US14098346

申请日：2013-12-05

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

公开(公告)号：US20150228777A1

公开(公告)日：2015-08-13

申请号：US14175308

申请日：2014-02-07

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78684 ,  H01L29/78696

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Abstract translation: 具有部分凹陷栅极的晶体管被​​构造在具有掩埋氧化物层（BOX）的例如FD-SOI和UTBB器件的绝缘体上硅（SOI）半导体晶片上。 外延生长的沟道区域放宽了掺杂源极和漏极配置图的限制。 部分凹入的栅极和升高的外延源极和漏极区域的形成允许晶体管性能的进一步改善和诸如漏极引起的栅极降低（DIBL）和特征亚阈值斜率的控制的短沟道效应的减少。 可以通过先进的过程控制辅助，改变栅极凹槽以使沟道相对于掺杂物分布形成不同的深度。 部分凹入的栅极具有最初形成为与栅极的三侧接触的相关联的高k栅极电介质。 随后去除高k侧壁和置换较低k氮化硅密封剂降低了栅极和源极和漏极区域之间的电容。

公开(公告)号：US20150162278A1

公开(公告)日：2015-06-11

申请号：US14098346

申请日：2013-12-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

公开(公告)号：US20150102496A1

公开(公告)日：2015-04-16

申请号：US14053531

申请日：2013-10-14

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal interconnections are formed in an integrated circuit by forming a wide trench in a dielectric layer. A dielectric fin of a second dielectric material is formed in the trench. Conductive plugs and metal lines are formed on both sides of the fin.

Abstract translation: 通过在电介质层中形成宽的沟槽，在集成电路中形成金属互连。 在沟槽中形成第二电介质材料的绝缘片。 导电插头和金属线形成在鳍的两侧。

公开(公告)号：US08970004B2

公开(公告)日：2015-03-03

申请号：US13725666

申请日：2012-12-21

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC: H01L29/00 ,  H01L27/02 ,  H01L21/266

CPC classification number: H01L27/0248 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/0255

Abstract: A junction diode array is disclosed for use in protecting integrated circuits from electrostatic discharge. The junction diodes integrate symmetric and asymmetric junction diodes of various sizes and capabilities. Some of the junction diodes are configured to provide low voltage and current discharge via un-encapsulated interconnecting wires, while others are configured to provide high voltage and current discharge via encapsulated interconnecting wires. Junction diode array elements include p-n junction diodes and N+/N++ junction diodes. The junction diodes include implanted regions having customized shapes. If both symmetric and asymmetric diodes are not needed as components of the junction diode array, the array is configured with isolation regions between diodes of either type. Some junction diode arrays include a buried oxide layer to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract translation: 公开了用于保护集成电路免受静电放电的结二极管阵列。 结二极管集成了各种尺寸和功能的对称和非对称结二极管。 一些结二极管被配置为通过未封装的互连线提供低电压和电流放电，而其它结构二极管被配置为通过封装的互连线提供高电压和电流放电。 结二极管阵列元件包括p-n结二极管和N + / N + +结二极管。 结二极管包括具有定制形状的植入区域。 如果不需要对称和非对称二极管作为结二极管阵列的组件，则阵列配置有任一类型的二极管之间的隔离区域。 一些结二极管阵列包括掩埋氧化物层，以防止掺杂剂扩散到超过选定深度的衬底中。

公开(公告)号：US20150053930A1

公开(公告)日：2015-02-26

申请号：US14464604

申请日：2014-08-20

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/51 ,  C23C14/048 ,  C23C14/221 ,  H01L21/02521 ,  H01L21/02631 ,  H01L21/28088 ,  H01L21/285 ,  H01L21/2855 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

Abstract translation: 通过在薄膜沉积期间控制簇的尺寸和电荷来调节含有分子簇的薄膜的能带。 使用原子层沉积，在纳米级晶体管的栅极区域中形成离子簇膜以调节阈值电压，并且在源极和漏极区域中形成中性聚集膜以调节接触电阻。 沉积诸如溴化银或氧化镧的功函半导体材料，以便包括由分离的单体形成的不同大小的簇，例如二聚体，三聚体和四聚体。 使用一种类型的原子层沉积系统沉积在半导体晶片分子簇上以形成具有选择的能隙的薄膜结。 离子束包含不同的离子簇，然后通过使光束通过过滤器而选择沉积，其中不同孔径基于尺寸和取向选择簇。

公开(公告)号：US20150002213A1

公开(公告)日：2015-01-01

申请号：US13931692

申请日：2013-06-28

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L23/525 ,  H01F17/02 ,  H01L49/02

CPC classification number: H01L23/5256 ,  H01F17/0006 ,  H01F17/02 ,  H01F2017/0073 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/5252 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract translation: 公开了纳米级电子元件，反熔丝和平面线圈电感器。 铜镶嵌工艺可用于制造所有这些电路元件。 可以使用低温铜蚀刻工艺来制造efuse和efuse样电感器。 电路元件可以通过以不同的配置和尺寸连接金属柱的矩阵来以模块化方式设计和构造。 金属柱的数量，或包括在电路元件中的电介质网的尺寸确定其电特性。 或者，电极和电感器可以由沉积在电介质柱的基体中的间隙金属形成，或者在蚀刻金属块中的柱状开口之后留下。 金属列的阵列还具有第二功能，作为可以改善抛光均匀性以代替常规虚拟结构的特征。 使用这种模块化阵列为集成电路设计人员提供了灵活性。

公开(公告)号：US20140353722A1

公开(公告)日：2014-12-04

申请号：US13907752

申请日：2013-05-31

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Cindy Goldberg ,  Walter Kleemeier

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.

Abstract translation: 公开了石墨烯封盖HEMT器件及其制造方法。 石墨烯封盖的HEMT器件包括一个或多个石墨烯帽，其增强用于高频，高能量应用（例如无线电信）中的示例性AlGaN / GaN异质结构晶体管的器件性能和/或可靠性。 所公开的HEMT装置利用石墨烯的非凡材料特性。 其中一个石墨烯帽作为晶体管下面的散热器，而另一个石墨烯帽稳定晶体管的源极，漏极和栅极区域，以防止在大功率操作期间的开裂。 公开了一种工艺流程，用于用原子厚的石墨烯层替代先前用于防止裂纹的三层膜堆，而不会使装置性能降低。 此外，所公开的HEMT器件包括六边形氮化硼粘附层，以便于将复合氮化物半导体沉积到石墨烯上。

公开(公告)号：US11948977B2

公开(公告)日：2024-04-02

申请号：US17852197

申请日：2022-06-28

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/10 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

公开(公告)号：US11063112B2

公开(公告)日：2021-07-13

申请号：US16164481

申请日：2018-10-18

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/28 ,  H01L49/02 ,  H01L27/11507

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.