Nonvolatile memory device made of resistance material and method of fabricating the same
    101.
    发明申请
    Nonvolatile memory device made of resistance material and method of fabricating the same 有权
    由电阻材料制成的非易失性存储器件及其制造方法

    公开(公告)号:US20110008945A1

    公开(公告)日:2011-01-13

    申请号:US12923429

    申请日:2010-09-21

    IPC分类号: H01L21/02

    摘要: A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, and an insulating layer is formed on the lower electrode to a predetermined thickness. The insulating layer has a contact hole exposing the lower electrode. A data storage layer is filled in the contact hole and the data storage layer is formed of transition metal oxide. An upper electrode is formed on the insulating layer and the data storage layer.

    摘要翻译: 提供了使用电阻材料的非易失性存储器件及其制造方法。 非易失性存储器件包括开关元件和电连接到开关元件的数据存储部件。 在数据存储部分中,下电极连接到开关元件,并且在下电极上形成预定厚度的绝缘层。 绝缘层具有暴露下电极的接触孔。 数据存储层填充在接触孔中,数据存储层由过渡金属氧化物形成。 在绝缘层和数据存储层上形成上电极。

    Semiconductor memory device with three dimensional solid electrolyte structure, and manufacturing method thereof
    102.
    发明申请
    Semiconductor memory device with three dimensional solid electrolyte structure, and manufacturing method thereof 失效
    具有三维固体电解质结构的半导体存储器件及其制造方法

    公开(公告)号:US20100190291A1

    公开(公告)日:2010-07-29

    申请号:US12662101

    申请日:2010-03-31

    IPC分类号: H01L21/02

    摘要: The semiconductor memory device includes a variable resistance device having a solid electrolyte in a three-dimensional structure. The variable resistance device includes a first electrode; the solid electrolyte, which has at least two regions with different heights, formed on the first electrode; and a second electrode made of a conductive material formed on the solid electrolyte to cover the regions with different heights. In addition, a multibit semiconductor memory device is provided which includes a bias circuit that can control the intensity of a current and time the current is supplied to the variable resistance device inside a memory cell in multiple steps to configure multibits.

    摘要翻译: 半导体存储器件包括具有三维结构的固体电解质的可变电阻器件。 可变电阻装置包括第一电极; 在第一电极上形成具有至少两个具有不同高度的区域的固体电解质; 以及由在固体电解质上形成的导电材料制成的第二电极,以覆盖不同高度的区域。 此外,提供了一种多位半导体存储器件,其包括偏置电路,该偏置电路可以在多个步骤中以多个步骤来控制电流的强度和电流被提供给存储器单元内的可变电阻器件的时间,以配置多个比特。

    Multi-bit memory device having reristive material layers as storage node and methods of manufacturing and operating the same
    103.
    发明申请
    Multi-bit memory device having reristive material layers as storage node and methods of manufacturing and operating the same 有权
    具有作为存储节点的重排材料层的多位存储器件及其制造和操作方法

    公开(公告)号:US20100187492A1

    公开(公告)日:2010-07-29

    申请号:US12662102

    申请日:2010-03-31

    申请人: Jung-hyun Lee

    发明人: Jung-hyun Lee

    IPC分类号: H01L45/00

    摘要: Provided are a multi-bit memory device having resistive material layers as a storage node, and methods of manufacturing and operating the same. The memory device includes a substrate, a transistor formed on the substrate, and a storage node coupled to the transistor, wherein the storage node includes: a lower electrode connected to the substrate; a first phase change layer formed on the lower electrode; a first barrier layer overlying the first phase change layer; a second phase change layer overlying the first barrier layer; and an upper electrode formed on the second phase change layer.

    摘要翻译: 提供了具有作为存储节点的电阻材料层的多位存储器件及其制造和操作方法。 存储器件包括衬底,形成在衬底上的晶体管和耦合到晶体管的存储节点,其中存储节点包括:连接到衬底的下电极; 形成在下电极上的第一相变层; 覆盖所述第一相变层的第一阻挡层; 覆盖第一阻挡层的第二相变层; 和形成在第二相变层上的上电极。

    Thin film including multi components and method of forming the same
    105.
    发明授权
    Thin film including multi components and method of forming the same 有权
    薄膜包括多组分及其形成方法

    公开(公告)号:US07709377B2

    公开(公告)日:2010-05-04

    申请号:US11176657

    申请日:2005-07-08

    IPC分类号: H01L21/469 H01L21/4763

    摘要: A thin film including multi components and a method of forming the thin film are provided, wherein a method according to an embodiment of the present invention, a substrate is loaded into a reaction chamber. A unit material layer is formed on the substrate. The unit material layer may be formed of a mosaic atomic layer composed of two kinds of precursors containing components constituting the thin film. The inside of the reaction chamber is purged, and the MAL is chemically changed. The method of forming the thin film of the present invention requires fewer steps than a conventional method while retaining the advantages of the conventional method, thereby allowing a superior thin film yield in the present invention than previously obtainable.

    摘要翻译: 提供了包括多组分的薄膜和形成薄膜的方法,其中根据本发明的实施方案的方法将基底装载到反应室中。 在基板上形成单位材料层。 单元材料层可以由包含构成薄膜的成分的两种前体构成的马赛克原子层形成。 反应室的内部被清除,并且MAL被化学地改变。 与传统方法相比,形成本发明的薄膜的方法需要更少的步骤,同时保持了常规方法的优点,从而使本发明的薄膜产率优于先前可获得的。

    Ge precursor, GST thin layer formed using the same, phase-change memory device including the GST thin layer, and method of manufacturing the GST thin layer
    106.
    发明授权
    Ge precursor, GST thin layer formed using the same, phase-change memory device including the GST thin layer, and method of manufacturing the GST thin layer 有权
    Ge前体,使用相同的GST薄层,包括GST薄层的相变存储器件,以及制造GST薄层的方法

    公开(公告)号:US07518007B2

    公开(公告)日:2009-04-14

    申请号:US11253693

    申请日:2005-10-20

    IPC分类号: C07F7/08 C07F7/00 C23C16/00

    摘要: Provided are a Ge precursor for low temperature deposition containing Ge, N, and Si, a GST thin layer doped with N and Si formed using the same, a memory device including the GST thin layer doped with N and Si, and a method of manufacturing the GST thin layer. The Ge precursor for low temperature deposition contains N and Si such that the temperature at which the Ge precursor is deposited to form a thin layer, particularly, the GST thin layer doped with N and Si, can be low. In addition, during the low temperature deposition, H2 plasma can be used. The GST phase-change layer doped with N and Si formed from the Ge precursor for low temperature deposition has a low reset current. Therefore, a memory device including the GST phase-change layer doped with N and Si can be highly integrated, have a high capacity, and can be operated at a high speed.

    摘要翻译: 提供了包含Ge,N和Si的低温沉积的Ge前体,掺杂有使用其形成的N和Si的GST薄层,包括掺杂有N和Si的GST薄层的存储器件,以及制造方法 GST薄层。 用于低温沉积的Ge前体包含N和Si,使得Ge前体沉积形成薄层的温度,特别是掺杂有N和Si的GST薄层的温度可以低。 此外,在低温沉积期间,可以使用H 2等离子体。 掺杂有由Ge前体形成的用于低温沉积的N和Si的GST相变层具有低复位电流。 因此,包含掺杂有N和Si的GST相变层的存储器件可以高度集成,具有高容量,并且可以高速运行。

    Ti precursor, method of preparing the same, method of preparing Ti-containing thin layer by employing the Ti precursor and Ti-containing thin layer
    107.
    发明授权
    Ti precursor, method of preparing the same, method of preparing Ti-containing thin layer by employing the Ti precursor and Ti-containing thin layer 有权
    Ti前体,其制备方法,采用Ti前体和含Ti薄层制备含Ti薄层的方法

    公开(公告)号:US07491347B2

    公开(公告)日:2009-02-17

    申请号:US11282486

    申请日:2005-11-21

    IPC分类号: H01B1/06 H01B1/02 C22C14/00

    摘要: A Ti-precursor for forming a Ti-containing thin layer represented by the formula I below, a method of preparing the same, a method of preparing a Ti-containing thin layer by employing the Ti-precursor and the Ti-containing thin layer are provided: wherein X1 and X2 are independently F, Cl, Br or I; n is 0, 1, 2, 3, 4 or 5; m is 0, 1, 2, 3, 4, 5, 6 or 7; and R1 and R2 are independently a linear or branched C1-10 alkyl group. The Ti precursor for forming the Ti-containing thin layer can be deposited at a deposition temperature of approximately 150° C.˜200° C., and a Ti-containing thin layer with a high performance character can be prepared.

    摘要翻译: 用于形成由下式I表示的含Ti薄层的Ti前体,其制备方法,通过使用Ti前体和含Ti薄层制备含Ti薄层的方法是 其中X1和X2独立地为F,Cl,Br或I; n为0,1,2,3,4或5; m为0,1,2,3,4,5,6或7; 并且R 1和R 2独立地为直链或支链C 1-10烷基。 用于形成含Ti薄层的Ti前体可以在约150℃〜200℃的沉积温度下沉积,并且可以制备具有高性能特征的含钛薄层。

    Method and apparatus for measuring signal quality using eye pattern
    109.
    发明授权
    Method and apparatus for measuring signal quality using eye pattern 有权
    使用眼图测量信号质量的方法和装置

    公开(公告)号:US07324903B2

    公开(公告)日:2008-01-29

    申请号:US10919531

    申请日:2004-08-17

    IPC分类号: G01R13/00 G06F11/30

    CPC分类号: H04L1/205

    摘要: A signal quality measuring method and apparatus in which a quality of a signal detected from an RF signal read out from a disk or a communications channel is measured by using eye pattern signals of the detected RF signals. Eye pattern signals representing time change of a waveform of the detected signal are generated and a signal quality value is generated based on an eye depth and/or an eye width measured from the eye pattern signals. A histogram of the eye pattern signals is used to identify a plurality of main level values which are used as a reference value in measuring the signal quality. Accordingly, signal characteristics in a high-density storage medium system or communication system may be accurately represented.

    摘要翻译: 一种信号质量测量方法和装置,其中通过使用检测到的RF信号的眼图信号测量从从盘或通信信道读出的RF信号中检测到的信号的质量。 产生表示检测信号的波形的时间变化的眼图信号,并且基于从眼图信号测量的眼睛深度和/或眼睛宽度来生成信号质量值。 眼图信号的直方图用于识别在测量信号质量时用作参考值的多个主电平值。 因此,可以精确地表示高密度存储介质系统或通信系统中的信号特性。