公开(公告)号：US20050026337A1

公开(公告)日：2005-02-03

申请号：US10628912

申请日：2003-07-28

申请人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

发明人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

IPC分类号： H01L21/332 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L29/66393 ,  H01L27/11

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P—N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在其上形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US06841441B2

公开(公告)日：2005-01-11

申请号：US10338156

申请日：2003-01-08

申请人： Chew Hoe Ang ,  Eng-Hua Lim ,  Randall Cher Liang Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

发明人： Chew Hoe Ang ,  Eng-Hua Lim ,  Randall Cher Liang Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

IPC分类号： H01L21/268 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49

CPC分类号： H01L29/4933 ,  H01L21/268 ,  H01L21/28061 ,  H01L21/823842

摘要： A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.

摘要翻译： 一种制造第一和第二栅极的方法，包括以下步骤。 提供了其上形成有栅介电层的基板。 衬底具有第一栅极区域和第二栅极区域。 在栅极电介质层上形成薄的第一栅极层。 第二栅极区域内的薄的第一栅极层被掩蔽以暴露第一栅极区域内的薄的第一栅极层的一部分。 薄的第一栅极层的暴露部分被转换成薄的第三栅极层部分。 在薄的第一和第三栅极层部分上形成第二栅极层。 第二栅极层和第一和第三栅极层部分被图案化以在第一栅极区域内形成第一栅极，在第二栅极区域内形成第二栅极。

公开(公告)号：US06709934B2

公开(公告)日：2004-03-23

申请号：US10196111

申请日：2002-07-16

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583

摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

摘要翻译： 一种形成具有不同介电常数区域的栅极电介质的方法。 在半导体结构上形成低K电介质层。 在低K电介质层上形成虚拟电介质层。 图案化虚拟介电层和低K电介质层以形成开口。 虚拟电介质层被选择性地蚀刻到低K电介质层以形成阶梯式栅极开口。 在虚拟电介质和阶梯式门开口中形成高K电介质层。 在高K电介质层上形成栅电极。

公开(公告)号：US06632712B1

公开(公告)日：2003-10-14

申请号：US10263895

申请日：2002-10-03

申请人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

发明人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

IPC分类号： H01L218238

CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L29/7827

摘要： A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.

摘要翻译： 已经开发了用于制造具有可变通道长度的垂直CMOS器件的工艺。 通道区域开口限定在复合绝缘体堆叠中，特定器件的通道长度由复合绝缘子堆叠的厚度确定。 在特定区域中选择性去除复合绝缘子堆叠的特定部件允许沟道开口的深度变化。 随后的外延硅生长过程填充可变深度通道开口，为垂直CMOS器件提供可变长度的沟道区。

公开(公告)号：US06566208B2

公开(公告)日：2003-05-20

申请号：US09912607

申请日：2001-07-25

申请人： Yang Pan ,  Lee Yong Meng ,  Leung Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundarensan

发明人： Yang Pan ,  Lee Yong Meng ,  Leung Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundarensan

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2257 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656

摘要： A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly doped regions using the gate electrode as a mask. Thereafter, dielectric spacers are formed on sidewalls of the gate electrode. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is etched back to leave polysilicon spacers on the dielectric spacers. Dopant is diffused from the polysilicon spacers into the semiconductor substrate to form source and drain regions underlying the polysilicon spacers. The polysilicon spacer on an end of the gate electrode is removed to separate the polysilicon spacers into a source polysilicon spacer and a drain polysilicon spacer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.

公开(公告)号：US06544848B1

公开(公告)日：2003-04-08

申请号：US10224212

申请日：2002-08-20

申请人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

发明人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L21/28273

摘要： A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer. A floating gate/control gate stack is formed overlying the second gate dielectric layer. One sidewall portion of the floating gate is covered with a mask. The second gate dielectric layer not covered by the mask is etched away whereby an undercut of the floating gate is formed in the second gate dielectric layer. The mask is removed. Polysilicon spacers are formed on sidewalls of the floating gate wherein one of the polysilicon spacers fills the undercut thereby forming a sharp polysilicon tip to improve the erase efficiency of the memory cell.

摘要翻译： 描述了在EEPROM存储器单元的制造中在浮动栅极上形成尖端尖端的新方法。 第一栅介质层设置在基板上。 第二栅介质层沉积在第一栅介质层上。 形成覆盖在第二栅极电介质层上的浮栅/控制栅叠层。 浮动栅极的一个侧壁部分被掩模覆盖。 被掩模未被覆盖的第二栅极电介质层被蚀刻掉，从而在第二栅极介质层中形成浮栅的底切。 去除面具。 多晶硅间隔物形成在浮置栅极的侧壁上，其中多晶硅间隔物中的一个填充底切，从而形成尖锐的多晶硅尖端，以提高存储单元的擦除效率。

公开(公告)号：US06511884B1

公开(公告)日：2003-01-28

申请号：US09972503

申请日：2001-10-09

申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/7827

摘要： A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a second implanted region is formed within the vertical pillar selected from the group consisting of a drain region and a source region that is not the same as the first implanted region to complete formation of the isolated vertical transistor.

摘要翻译： 一种制造隔离垂直晶体管的方法，包括以下步骤。 提供具有从包括源极区域和漏极区域的组中选择的第一注入区域的晶片。 该晶片还包括在中心晶体管区域两侧的STI区域。 将晶片图案化到第一注入区域，以使用图案化的硬掩模在中心晶体管区域内形成垂直柱。 具有侧壁的立柱。 在晶片上形成衬垫介质层，衬在垂直柱上。 在焊盘介电层上形成氮化物层。 该结构被图案化并蚀刻通过氮化物层和焊盘介电层; 并进入STI区域内的晶片，以在晶片内形成STI沟槽。 STI沟槽填充有绝缘材料，以在STI沟槽内形成STI。 图案化的氮化物和焊盘介电层被去除。 去除图案化的硬掩模。 栅极氧化物生长在晶片和垂直柱的暴露部分上。 在垂直柱的栅极氧化物衬里侧壁上形成间隔栅极。 间隔栅极内部形成间隔栅极，并且在垂直柱内形成第二注入区，该垂直柱选自由漏极区域和不同于第一注入区域的源极区域组成的组，以完成孤立的 垂直晶体管。

公开(公告)号：US06417054B1

公开(公告)日：2002-07-09

申请号：US09769830

申请日：2001-01-26

申请人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

发明人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L21366

CPC分类号： H01L29/6653 ,  H01L21/76232 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66636

摘要： A method for a self aligned TX with elevated source/drain (S/D) regions on an insulated layer (oxide) by forming a trench along side the STI and filling the trench with oxide. STI regions are formed in a substrate. A gate structure is formed. LDD regions are formed adjacent to the gate structure in the substrate. Spacers are formed on the sidewall of the gate structure. We etch S/D trenches between the STI regions and the first spacers. The S/D trenches are filled with a S/D insulating layer. Elevated S/D regions are formed over the S/D insulating layer and the LDD regions. A top isolation layer is formed over the STI regions. The invention builds the raised source/drain (S/D) regions on an insulating layer and reduces junction leakage and hot carrier degradation to gate oxide.

摘要翻译： 一种通过在STI侧面形成沟槽并用氧化物填充沟槽，在绝缘层（氧化物）上具有升高的源极/漏极（S / D）区域的自对准TX的方法。 STI区域形成在基板中。 形成栅极结构。 在基板中与栅极结构相邻地形成LDD区域。 隔板形成在栅极结构的侧壁上。 我们蚀刻STI区域和第​​一间隔物之间​​的S / D沟槽。 S / D沟槽填充有S / D绝缘层。 在S / D绝缘层和LDD区域上形成升高的S / D区域。 在STI区域上形成顶部隔离层。 本发明在绝缘层上构建了凸起的源极/漏极（S / D）区域，并减少了结合漏电和热载流子对栅极氧化物的降解。

公开(公告)号：US06380088B1

公开(公告)日：2002-04-30

申请号：US09764241

申请日：2001-01-19

申请人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

发明人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

IPC分类号： H01L21302

CPC分类号： H01L29/66583 ,  H01L21/76224 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636

摘要： An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed in the shallow trench isolations, which exposes sidewall of the substrate in the active area. Sidewalls of the substrate are doped in the active area where holes are. Conductive material is then formed in the holes and the conductive material becomes the source and drain regions. The etch stop layer is then removed exposing sidewalls of the conductive material, and oxidizing exposed sidewalls of the conductive material is preformed. Spacers are formed on top of the pad oxide and on the sidewalls of the oxidized portions of the conductive material. The pad oxide layer is removed from the structure but not from under the spacers. A gate dielectric layer is formed on the substrate in the active area between the spacers; and a gate electrode is formed on said gate dielectric layer.

摘要翻译： 一种改进的MOS晶体管和制造改进的MOS晶体管的方法。 MOS晶体管，具有沟槽侧壁上的凹陷源极漏极，具有替代栅极技术。 在浅沟槽隔离件中形成孔，其在有源区域中暴露衬底的侧壁。 在孔的有源区域中掺杂衬底的侧壁。 然后在孔中形成导电材料，并且导电材料变成源区和漏区。 然后去除蚀刻停止层，暴露导电材料的侧壁，并且对导电材料的暴露侧壁进行氧化预处理。 垫片形成在衬垫氧化物的顶部和导电材料的氧化部分的侧壁上。 衬垫氧化物层从结构中移除，但不从衬垫下方移除。 在间隔物之间​​的有源区域中的基板上形成栅极电介质层; 并且在所述栅极电介质层上形成栅电极。

公开(公告)号：US06306715B1

公开(公告)日：2001-10-23

申请号：US09756008

申请日：2001-01-08

申请人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

发明人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

IPC分类号： H01L21336

CPC分类号： H01L21/32136 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/6659

摘要： A method to form a MOS transistor with a narrow channel regions and a wide top (second) gate portion. A gate dielectic layer and a first gate layer are formed over a substrate. A second gate portion is formed over the first gate layer. Spacers are formed on the sidewalls of the second gate portion. In a critical step, we isotropically etch the first gate layer to undercut the second gate portion to form a first gate portion so that the first portion has a width less than the second gate portion. The spacers are removed. Lightly doped drains, sidewall spacers and source/drain regions are formed to complete the device.

摘要翻译： 一种形成具有窄沟道区和宽顶（第二）栅极部分的MOS晶体管的方法。 在衬底上形成栅极介电层和第一栅极层。 第二栅极部分形成在第一栅极层上。 间隔件形成在第二栅极部分的侧壁上。 在关键步骤中，我们对第一栅极层进行各向同性蚀刻，以切割第二栅极部分以形成第一栅极部分，使得第一部分具有小于第二栅极部分的宽度。 去除间隔物。 形成轻掺杂的漏极，侧壁间隔物和源极/漏极区以完成该器件。