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17 条记录 (耗时 0.037 秒)

    Method of fabricating variable length vertical transistors
    1.
    发明授权
    Method of fabricating variable length vertical transistors 失效
    制造可变长度垂直晶体管的方法

    公开(公告)号：US06632712B1

    公开(公告)日：2003-10-14

    申请号：US10263895

    申请日：2002-10-03

    申请人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L218238

    CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L29/7827

    摘要： A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.

    摘要翻译： 已经开发了用于制造具有可变通道长度的垂直CMOS器件的工艺。 通道区域开口限定在复合绝缘体堆叠中，特定器件的通道长度由复合绝缘子堆叠的厚度确定。 在特定区域中选择性去除复合绝缘子堆叠的特定部件允许沟道开口的深度变化。 随后的外延硅生长过程填充可变深度通道开口，为垂直CMOS器件提供可变长度的沟道区。

    Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers
    2.
    发明授权
    Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers 失效
    使用小的原位掺杂多晶硅间隔物形成非对称非易失性存储器件的方法

    公开(公告)号：US06544848B1

    公开(公告)日：2003-04-08

    申请号：US10224212

    申请日：2002-08-20

    申请人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    发明人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L218247

    CPC分类号： H01L29/66825 ,  H01L21/28273

    摘要： A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer. A floating gate/control gate stack is formed overlying the second gate dielectric layer. One sidewall portion of the floating gate is covered with a mask. The second gate dielectric layer not covered by the mask is etched away whereby an undercut of the floating gate is formed in the second gate dielectric layer. The mask is removed. Polysilicon spacers are formed on sidewalls of the floating gate wherein one of the polysilicon spacers fills the undercut thereby forming a sharp polysilicon tip to improve the erase efficiency of the memory cell.

    摘要翻译： 描述了在EEPROM存储器单元的制造中在浮动栅极上形成尖端尖端的新方法。 第一栅介质层设置在基板上。 第二栅介质层沉积在第一栅介质层上。 形成覆盖在第二栅极电介质层上的浮栅/控制栅叠层。 浮动栅极的一个侧壁部分被掩模覆盖。 被掩模未被覆盖的第二栅极电介质层被蚀刻掉，从而在第二栅极介质层中形成浮栅的底切。 去除面具。 多晶硅间隔物形成在浮置栅极的侧壁上，其中多晶硅间隔物中的一个填充底切，从而形成尖锐的多晶硅尖端，以提高存储单元的擦除效率。

    Method to pattern small features by using a re-flowable hard mask
    3.
    发明授权
    Method to pattern small features by using a re-flowable hard mask 有权
    通过使用可重新流动的硬掩模来绘制小特征的方法

    公开(公告)号：US06828082B2

    公开(公告)日：2004-12-07

    申请号：US10072102

    申请日：2002-02-08

    申请人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    IPC分类号： G03F700

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/31144

    摘要： A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.

    摘要翻译： 一种形成小特征的方法，包括以下步骤。 提供其上形成有介电层的基板。 在电介质层上形成间隔层。 间隔层的厚度等于要形成的小特征的厚度。 在间隔层上形成图案化的可重新流动的掩模层。 掩模层具有宽度“L”的第一开口。 图案化的可再流过的掩模层被再流动以形成具有较低宽度“1”的具有再流动的第一开口的图案化的再流过的掩蔽层。 再流通的第一开口下部宽度“1”小于预先回流的第一开口宽度“L”。 使用图案化的再流过的掩模层作为掩模将间隔层蚀刻到介电层，以在蚀刻的间隔层内形成具有等于再流动的第一开口下宽度“1”的宽度的第二开口。 去除图案化的再流过的掩蔽层。 然后在第二开口内形成小的特征材料，并且去除蚀刻的间隔层上方的任何过量的小特征材料。 蚀刻的间隔层被去除以形成由小特征材料组成的小特征。

    Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask
    4.
    发明授权
    Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask 有权
    通过使用自对准反向间隔件作为硬掩模形成小晶体管栅极的方法

    公开(公告)号：US06610604B1

    公开(公告)日：2003-08-26

    申请号：US10068053

    申请日：2002-02-05

    申请人： Chew-Hoe Ang ,  Eng-Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng-Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L21302

    CPC分类号： H01L21/28132

    摘要： A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.

    摘要翻译： 一种形成窄门的方法，包括以下步骤。 提供具有覆盖的Si 3 N 4或SiO 2 / Si 3 N 4堆叠栅极介电层的衬底。 栅极材料层形成在栅极介电层上。 在栅极材料层上形成硬掩模层。 图案化硬掩模层和栅极材料层以形成硬掩模/栅极材料层堆叠。 形成围绕硬掩模/栅极材料层叠层的平坦化介电层。 图案化的硬掩模层从图案化的栅极材料层上去除以形成具有暴露的电介质层侧壁的空腔。 屏蔽间隔物形成在图案化栅极材料层的一部分上的暴露的电介质层侧壁上。 使用掩模间隔物作为掩模蚀刻图案化的栅极材料层，以露出栅极电介质层的一部分。 去除平坦化的介电层。 去除掩模间隔物以形成包括栅极材料的窄门。

    Forming dual gate oxide thickness on vertical transistors by ion implantation
    6.
    发明授权
    Forming dual gate oxide thickness on vertical transistors by ion implantation 有权
    通过离子注入在垂直晶体管上形成双栅氧化层厚度

    公开(公告)号：US06610575B1

    公开(公告)日：2003-08-26

    申请号：US10161818

    申请日：2002-06-04

    申请人： Chew-Hoe Ang ,  Eng-Hua Lim ,  Cher-Liang Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng-Hua Lim ,  Cher-Liang Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L218234

    CPC分类号： H01L21/823857 ,  H01L21/823885

    摘要： A method of structures having dual gate oxide thicknesses, comprising the following steps. A substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the outer or inner side walls of at least one of the first and second pillars is/are masked leaving at least one of the outer or inner side walls of at least one of the first and second pillars exposed. Dopants are then implanted through the at least one of the exposed outer or inner side walls modifying the surface of the at least one of the doped exposed outer or inner side walls. The at least one of the masked outer or inner side walls of at least one of the first and second pillars is/are unmasked. Gate oxide is grown on the outer side walls and the inner side walls of the first and second pillars wherein the gate oxide grown upon the modified surfaces of the at least one of the doped outer or inner side walls is thicker than the gate oxide grown upon the non-modified surfaces of the at least one of the non-doped outer or inner side walls.

    摘要翻译： 一种具有双栅极氧化物厚度的结构的方法，包括以下步骤。 提供具有第一和第二柱的衬底。 第一和第二支柱各自具有外侧壁和内侧壁。 至少一个第一和第二支柱的外侧壁或内侧壁中的至少一个被遮蔽，留下第一和第二柱中的至少一个的至少一个外壁或内侧壁暴露。 然后通过暴露的外侧壁或内侧壁中的至少一个植入掺杂剂，改变掺杂的暴露的外壁或内侧壁中的至少一个的表面。 第一和第二支柱中的至少一个的被掩蔽的外侧壁或内侧壁中的至少一个被遮蔽。 栅极氧化物生长在第一和第二柱的外侧壁和内侧壁上，其中生长在掺杂的外壁或内侧壁中的至少一个的改性表面上的栅极氧化物比生长在栅极氧化物上的栅极氧化物厚 所述非掺杂外侧壁或内侧壁中的至少一个的未修饰表面。

    Method to pattern small features by using a re-flowable hard mask
    9.
    发明申请
    Method to pattern small features by using a re-flowable hard mask 审中-公开
    通过使用可再流动的硬掩模来绘制小特征的方法

    公开(公告)号：US20050089777A1

    公开(公告)日：2005-04-28

    申请号：US10988349

    申请日：2004-11-12

    申请人： Chew-Hoe Ang ,  Eng Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    IPC分类号： G03C5/00 ,  G03F7/00 ,  G03F7/26 ,  H01L21/033 ,  H01L21/311 ,  H01L21/76

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/31144

    摘要： A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “l”. The re-flowed first opening lower width “l” being less than the pre-re-flowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “l”. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.

    摘要翻译： 一种形成小特征的方法，包括以下步骤。 提供其上形成有介电层的基板。 在电介质层上形成间隔层。 间隔层的厚度等于要形成的小特征的厚度。 在间隔层上形成图案化的可重新流动的掩模层。 掩模层具有宽度“L”的第一开口。 图案化的可重新流动的掩模层被再流动以形成具有较低宽度“l”的具有再流动的第一开口的图案化的再流过的掩蔽层。 再流出的第一开口下部宽度“l”小于预先流动的第一开口宽度“L”。 使用图案化的再流过的掩模层作为掩模将间隔层蚀刻到介电层上，以在蚀刻的间隔层内形成具有等于再流动的第一开口下宽度“l”的宽度的第二开口。 去除图案化的再流过的掩蔽层。 然后在第二开口内形成小的特征材料，并且去除蚀刻的间隔层上方的任何过量的小特征材料。 蚀刻的间隔层被去除以形成由小特征材料组成的小特征。