公开(公告)号：US11342193B2

公开(公告)日：2022-05-24

申请号：US17034043

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun Liu ,  Chih-Ming Lai ,  Wei-Liang Lin ,  Yung-Sung Yen ,  Ken-Hsien Hsieh ,  Chin-Hsiang Lin

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

公开(公告)号：US11320747B2

公开(公告)日：2022-05-03

申请号：US17121542

申请日：2020-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shinn-Sheng Yu ,  Ru-Gun Liu ,  Hsu-Ting Huang ,  Kenji Yamazoe ,  Minfeng Chen ,  Shuo-Yen Chou ,  Chin-Hsiang Lin

IPC: G03F7/20

Abstract: Photolithography apparatus includes a radiation source, a mask to modify radiation from the radiation source so the radiation exposes photoresist layer disposed on a semiconductor substrate in patternwise manner, a wafer stage, and a controller. The wafer stage supports the semiconductor substrate. The controller determines target total exposure dose for the photoresist layer and target focus position for the photoresist layer; and controls exposure of first portion of the photoresist layer to first exposure dose of radiation at first focus position using first portion of the mask, moving the semiconductor substrate relative to the mask; and exposure of the first portion of the photoresist layer to second exposure dose of radiation using second portion of the mask at second focus position, and exposure of second portion of the photoresist layer to the second exposure dose at the second focus position using the first portion of the mask.

公开(公告)号：US11294286B2

公开(公告)日：2022-04-05

申请号：US16287450

申请日：2019-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun Liu ,  Chin-Hsiang Lin ,  Cheng-I Huang ,  Chih-Ming Lai ,  Chien-Wen Lai ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Yuan-Te Hou

IPC: G03F7/20 ,  G03F1/42 ,  G03F1/68 ,  G03F1/50

Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

公开(公告)号：US11289376B2

公开(公告)日：2022-03-29

申请号：US16892984

申请日：2020-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Gun Liu ,  Shih-Ming Chang ,  Hoi-Tou Ng

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522

Abstract: The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.

公开(公告)号：US11158509B2

公开(公告)日：2021-10-26

申请号：US16877755

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/033

Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.

公开(公告)号：US20210280607A1

公开(公告)日：2021-09-09

申请号：US17328534

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang CHEN ,  Cheng-Chi Chuang ,  Chih-Ming Lai ,  Chia-Tien Wu ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Ru-Gun Liu ,  Wei-Cheng Lin ,  Lei-Chun Chou ,  Wei-An Lai

IPC: H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/02

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

公开(公告)号：US11079685B2

公开(公告)日：2021-08-03

申请号：US15966962

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Wei-Shuo Su

IPC: G03F7/00 ,  G03F7/20 ,  H01L21/311 ,  G03F1/36 ,  G03F1/70 ,  G06F30/398 ,  G06F119/18

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

公开(公告)号：US11075079B2

公开(公告)日：2021-07-27

申请号：US16107699

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chun Huang ,  Ya-Wen Yeh ,  Chien Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Ru-Gun Liu ,  Chin-Hsiang Lin ,  Yu-Tien Shen

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/308 ,  H01L21/266 ,  C23C16/458 ,  C23C16/50 ,  C23C16/04

Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.

公开(公告)号：US11043381B2

公开(公告)日：2021-06-22

申请号：US16258656

申请日：2019-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Li-Te Lin ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Pinyen Lin ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

公开(公告)号：US11024579B2

公开(公告)日：2021-06-01

申请号：US16382478

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Yung-Sung Yen

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.