摘要:
There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock signals having an almost equal phase difference from each other and a jitter injecting section for injecting jitter into the respective clock signals.
摘要:
A testing apparatus tests the performance of an electronic device having an operation circuit for providing a useful output signal. A demodulator configured to provide a phase or frequency demodulated signal related to the output of the operation circuit is packaged with the operation circuit. The gain of the demodulator is controllable from outside the package. The testing apparatus analyses the demodulated signal and controls the gain of the demodulator.
摘要:
An air conditioner includes a pipe volume calculating section and a refrigerant circuit configured by the interconnection of a heat source unit and a utilization unit via a refrigerant communication pipe. The pipe volume calculating section calculates the volume of the refrigerant communication pipe based on an additional charging quantity which is a refrigerant quantity to be additionally charged after the refrigerant circuit is configured by interconnecting the heat source unit and the utilization unit via the refrigerant communication pipe.
摘要:
The curvature of a circular arc constituted by a side of a suction groove is made larger than that of a circular arc constituted by a side of a discharge groove. Thus, when the suction groove and the discharge groove are viewed in the axial direction of a drive shaft, the distance between the suction groove and the discharge groove in the radial direction of a rotary portion is short in a region intersecting with a line W perpendicular to a centerline, and increases in accordance with a decrease in distance from containment portions. It is therefore possible to ensure a sufficient distance between the discharge and suction grooves and enhance a total fluid pressure generated therebetween, and the contact surface pressure that is necessitated by a second side plate to obtain a press-back force when being in contact with an outer rotor and an inner rotor is reduced.
摘要:
There is provided a measuring apparatus for measuring a signal-under-test, having a comparator for sequentially comparing voltage values of the signal-under-test with a reference voltage value fed thereto at timing of strobe signals sequentially fed thereto, a strobe timing generator for sequentially generating the strobe signals placed almost at equal time intervals, a capture memory for storing the comparison result of the comparator and a digital signal processing section for calculating jitter of the signal-under-test based on the comparison result stored in the capture memory.
摘要:
A measuring apparatus that measures signal-under-test of which signal level is changed at a predetermined bit time interval is provided. The measuring apparatus includes: a strobe timing generator that sequentially generates strobes arranged at substantially even time intervals; a level comparison section that detects the level of the signal-under-test at a timing at which each strobe is sequentially provided; a capture memory that stores therein the signal level outputted by the level comparison section; and a digital signal processing section that calculates a measurement result of the signal-under-test based on data series including data which have substantially even time intervals and each of which interval is larger than a bit time interval of the signal-under-test. The measuring apparatus may include a logical comparison section that outputs a comparison result indicating whether the logical value detected by the level comparison section is corresponding to an expected value and a memory that stores therein the comparison result outputted by the logical comparison section instead of the capture memory. In this case, the digital signal processing section derives the measurement result of the signal-under-test from the comparison result stored in the memory.
摘要:
A wideband signal analyzing apparatus for analyzing an input signal includes frequency-shifting means for generating a plurality of intermediate frequency signals by shifting a frequency of the input signal as much as respectively different frequency-shifting amounts, so that if a frequency band of the input signal is divided into a plurality of frequency bands, each of the frequency bands can be shifted to a predetermined intermediate band, spectrum measuring means for outputting a complex spectrum of each of the intermediate frequency signals, and spectrum reconstructing means for merging the complex spectra.
摘要:
A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.
摘要:
A test pattern sequence to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by an implication operation. A propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by another implication operation. A sequence formed by v1 and v2 is registered with a test pattern list and the described operations are repeated until there remains no unprocessed fault in the fault list.