公开(公告)号：US20120319721A1

公开(公告)日：2012-12-20

申请号：US13587827

申请日：2012-08-16

申请人： Kleanthes G. Koniaris ,  James B. Burr

发明人： Kleanthes G. Koniaris ,  James B. Burr

IPC分类号： G01R31/26

CPC分类号： H03K3/012 ,  G01R31/2621 ,  G05B13/021 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H03K3/0315 ,  Y02D10/126 ,  Y02D10/172

摘要： Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.

摘要翻译： 集成电路闭环反馈控制系统与方法。 在一个实施例中，调整集成电路的多个可控输入以实现集成电路的动态工作指示器的预定值。 基于集成电路行为的动态操作指示灯，通过闭环反馈来控制集成电路的工作状态。

公开(公告)号：US08222914B2

公开(公告)日：2012-07-17

申请号：US12547392

申请日：2009-08-25

申请人： Robert Paul Masleid ,  James B. Burr

发明人： Robert Paul Masleid ,  James B. Burr

IPC分类号： G01R31/26

CPC分类号： H03K19/0027 ,  G01R31/2621 ,  H03K2217/0018

摘要： Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.

摘要翻译： 用于调整阈值电压的系统和方法。 测量集成电路的晶体管的阈值电压。 当施加到晶体管的体阱时，偏置电压校正阈值电压和晶体管的期望阈值电压之间的差异。 偏置电压被编码到集成电路上的非易失性存储器中。 非易失性存储器可以是数字和/或模拟的。

公开(公告)号：US20120001651A1

公开(公告)日：2012-01-05

申请号：US13235301

申请日：2011-09-16

申请人： Kleanthes G. Koniaris ,  James B. Burr

发明人： Kleanthes G. Koniaris ,  James B. Burr

IPC分类号： G01R31/02

CPC分类号： H03K3/012 ,  G01R31/2621 ,  G05B13/021 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H03K3/0315 ,  Y02D10/126 ,  Y02D10/172

摘要： Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies.An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.

摘要翻译： 用于集成电路的频率特定闭环反馈控制的系统和方法。 在一个实施例中，调整集成电路的多个可控制输入以在期望的特定工作频率下实现集成电路的动态工作指示器的频率特定预定值。 预定值被存储在计算机可用媒体内的数据结构中。 数据结构包括用于各种工作频率的多个特定于频率的预定值。 基于集成电路的测量行为的动态操作指示灯，通过闭环反馈控制集成电路的工作状态。

公开(公告)号：US08003471B2

公开(公告)日：2011-08-23

申请号：US12715262

申请日：2010-03-01

申请人： James B. Burr ,  Archisman Bagchi ,  Jawad Nasrullah

发明人： James B. Burr ,  Archisman Bagchi ,  Jawad Nasrullah

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/7833

摘要： Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

摘要翻译： 具有超陡逆行通道的升高源/漏源的系统和方法。 根据本发明的第一实施例，在一个实施例中，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面上方的栅极氧化物。 半导体器件还包括形成在表面下方深度的超陡逆行通道区域。 深度约为栅极氧化物厚度的十至三十倍。 根据一个实施例的实施例可以提供比常规技术中可用的更理想的主体偏置电压到阈值电压特性。

公开(公告)号：US07996809B2

公开(公告)日：2011-08-09

申请号：US12033832

申请日：2008-02-19

申请人： David R. Ditzel ,  James B. Burr

发明人： David R. Ditzel ,  James B. Burr

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.

摘要翻译： 软件控制晶体管体偏置。 访问目标频率。 使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。 晶体管的主体基于主体偏置值被偏置，其中特性被增强。

公开(公告)号：US07941675B2

公开(公告)日：2011-05-10

申请号：US10334918

申请日：2002-12-31

申请人： James B. Burr ,  Andrew Read ,  Tom Stewart

发明人： James B. Burr ,  Andrew Read ,  Tom Stewart

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method and system of adaptive power control. Characteristics of a specific integrated circuit are used to adaptively control power of the integrated circuit.

摘要翻译： 一种自适应功率控制的方法和系统。 特定集成电路的特性用于自适应地控制集成电路的功率。

公开(公告)号：US07917772B1

公开(公告)日：2011-03-29

申请号：US11529865

申请日：2006-09-29

申请人： Kleanthes G. Koniaris ,  James B. Burr ,  Mark Hennecke

发明人： Kleanthes G. Koniaris ,  James B. Burr ,  Mark Hennecke

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G05B13/026 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

摘要： Methods and systems for operating a semiconductor device (e.g., a microprocessor) are described. The microprocessor is initially operated at a voltage and frequency that would be within operating limits at any device temperature. Using models that relate device temperature, operating limits and power consumption with voltage and frequency, the amount of supply voltage and a new operating frequency can be selected. The models are periodically consulted thereafter to continue adjusting the supply voltage and operating frequency, so that the microprocessor is caused to operate at very close to its capacity, in particular in those instances when, for example, processor-intensive instructions are being executed.

摘要翻译： 描述了用于操作半导体器件（例如，微处理器）的方法和系统。 微处理器最初以在任何器件温度下处于操作限度内的电压和频率运行。 使用将设备温度，工作限制和功耗与电压和频率相关联的型号，可以选择电源电压和新的工作频率。 此后，定期咨询这些型号以继续调整电源电压和工作频率，以使微处理器在非常接近其容量的情况下工作，特别是在例如执行处理器密集型指令的情况下。

公开(公告)号：US07859062B1

公开(公告)日：2010-12-28

申请号：US10956722

申请日：2004-09-30

申请人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

发明人： Kleanthes G. Koniaris ,  Robert Paul Masleid ,  James B. Burr

IPC分类号： H01L29/72

CPC分类号： H03K19/0027 ,  H03K2217/0018

摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.

摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据本发明的第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。

公开(公告)号：US07747974B1

公开(公告)日：2010-06-29

申请号：US11649443

申请日：2007-01-03

申请人： James B. Burr ,  William N. Schnaitter

发明人： James B. Burr ,  William N. Schnaitter

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method and apparatus for optimizing body bias connections to NFETs and PFETs using a deep n-well grid structure. A deep n-well is formed below the surface of a CMOS substrate supporting a plurality of NFETs and PFETs having a nominal gate length of less than 0.2 microns. The deep n-well is a grid structure with a regular array of apertures providing electrical continuity between the bottom of the substrate and the NFETs. The PFETs reside in surface n-wells that are continuous with the buried n-well grid structure. The grid and n-well layout is performed on the basis of the functionality of the PFETs contained in the n-wells.

摘要翻译： 一种用于优化使用深n阱栅格结构的NFET和PFET的体偏置连接的方法和装置。 在支撑多个NFET和具有小于0.2微米的标称栅极长度的PFET的CMOS衬底的表面下方形成深n阱。 深n阱是具有规则的孔阵列的栅格结构，其在衬底的底部和NFET之间提供电连续性。 PFET位于与埋置的n阱栅格结构连续的表面n阱中。 栅极和n阱布局基于n阱中包含的PFET的功能进行。

公开(公告)号：US20080144407A1

公开(公告)日：2008-06-19

申请号：US12037884

申请日：2008-02-26

申请人： Robert P. Masleid ,  James B. Burr

发明人： Robert P. Masleid ,  James B. Burr

IPC分类号： G11C7/00 ,  G06F17/50

CPC分类号： H03K5/1252 ,  H03K5/133 ,  H03K17/6872 ,  H03K19/00361

摘要： Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.

摘要翻译： 堆叠式逆变器延时链。 根据本发明的第一实施例，两个p型器件的串联堆叠耦合到三个n型器件的串联堆叠，形成堆叠的反相器，其包括期望的延迟，管芯面积和功率特性。 两个堆叠的反相器耦合在一起以形成堆叠的反相器延迟链，其在与常规逆变器的常规延迟链相比在管芯面积，主动和无源功耗方面更有效。