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    METHOD FOR FORMING DYNAMIC RANDOM ACCESS MEMORY STRUCTURE
    101.
    发明申请
    METHOD FOR FORMING DYNAMIC RANDOM ACCESS MEMORY STRUCTURE 审中-公开

    公开(公告)号：US20200013783A1

    公开(公告)日：2020-01-09

    申请号：US16571202

    申请日：2019-09-16

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang ,  Sho-Shen Lee

    IPC: H01L27/108 ,  G11C11/401

    Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    102.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20190341487A1

    公开(公告)日：2019-11-07

    申请号：US16509475

    申请日：2019-07-11

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

    IPC: H01L29/78 ,  H01L27/108 ,  H01L21/02 ,  H01L21/762 ,  H01L21/4757

    Abstract: A method of forming a semiconductor structure is disclosed, comprising providing a substrate, forming at least a gate trench extending along a first direction in the substrate, forming a gate dielectric layer conformally covering the gate trench, forming a sacrificial layer on the gate dielectric layer and completely filling the gate trench, forming a plurality of openings through the sacrificial layer in the gate trench thereby exposing a portion of the gate dielectric layer, forming a dielectric material in the openings, performing an etching back process to remove a portion of the dielectric material until the dielectric material only remains at a lower portion of each of the openings thereby obtaining a plurality of intervening structures, removing the sacrificial layer, and forming a gate metal filling the gate trench, wherein the intervening structures are disposed between the gate metal and the gate dielectric layer.

    Manufacturing method of oxide semiconductor device
    104.
    发明授权
    Manufacturing method of oxide semiconductor device 有权

    公开(公告)号：US10403743B2

    公开(公告)日：2019-09-03

    申请号：US15655881

    申请日：2017-07-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Xiang Li ,  Shao-Hui Wu ,  Hsiao Yu Chia ,  Yu-Cheng Tung

    IPC: H01L29/786 ,  H01L29/66 ,  H01L21/465

    Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process.

    Semiconductor device having gate structure
    107.
    发明授权
    Semiconductor device having gate structure 有权

    公开(公告)号：US10319641B2

    公开(公告)日：2019-06-11

    申请号：US16127241

    申请日：2018-09-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： En-Chiuan Liou ,  Chao-Hung Lin ,  Yu-Cheng Tung

    IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L21/308 ,  H01L29/06 ,  H01L21/28 ,  H01L29/66

    Abstract: A semiconductor device includes a substrate, a first insulating structure and a gate structure. The substrate includes at least two fin structures protruding from a top surface of the substrate, the substrate includes a first recess and a second recess under the first recess, and the first recess and the second recess are disposed between the fin structures, in which a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure. The first insulating structure fills the second recess. The gate structure is disposed on the first insulating structure, in which the first recess and the second recess are filled up with the gate structure and the first insulating structure.

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