公开(公告)号：US10747681B1

公开(公告)日：2020-08-18

申请号：US16356016

申请日：2019-03-18

申请人： Arm Limited

发明人： Håkan Lars-Göran Persson

IPC分类号： G06F12/10 ,  G06F12/1018 ,  G06F12/0891 ,  G06F12/1045 ,  G06F12/0808

摘要： Apparatuses and methods for address translation invalidation are provided. In an apparatus having address translation storage which stores merged address translation information for multiple address translation stages, a set of counters are provided to hold a set of counter values. Entries in the address translation storage are stored with identifiers of first and second counters selected from the set of counters in dependence on respective context information for a first stage and a second stage of address translation together with a counter value of each counter. In response to an invalidation request specifying a first or second addressing scheme invalidation context a counter of the set of counters is selected in dependence on the first or second addressing scheme invalidation context and its value is modified. Subsequently an entry in the address translation storage is determined to be invalid when either the first counter value does not match a current value of the first counter or the second counter value does not match a current value of the second counter.

公开(公告)号：US10713168B2

公开(公告)日：2020-07-14

申请号：US15844084

申请日：2017-12-15

申请人： International Business Machines Corporation

发明人： Christian Jacobi ,  Ulrich Mayer ,  Martin Recktenwald ,  Anthony Saporito ,  Aaron Tsai

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/0831 ,  G06F12/1045 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/1027

摘要： Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：US10691608B2

公开(公告)日：2020-06-23

申请号：US15851775

申请日：2017-12-22

申请人： Jaesop Kong

发明人： Jaesop Kong

IPC分类号： G06F12/08 ,  G06F12/0882 ,  G06F3/06 ,  G11C8/10 ,  G11C8/12 ,  G11C7/12 ,  G11C7/10 ,  G06F13/16 ,  G06F12/1045 ,  G06F12/02

摘要： A memory device includes a memory cell array, a row decoder, a multi-column decoder, a gating circuit, and an input/output data driving circuit. The memory cell array includes a plurality of memory cells arranged to form a plurality of rows and a plurality of columns. The row decoder generates a row selection signal based on a row address to select a target row from the rows. The multi-column decoder generates a multi-column selection signal based on a column address and column selection information to select a plurality of target columns from columns included in the target row at a time. The gating circuit selects the target columns at a time based on the multi-column selection signal. The input/output data driving circuit writes input data to the target columns at a time or outputs data stored in the target columns at a time as output data through the gating circuit based on the multi-column selection signal and a data mask signal. Column addresses corresponding to the target columns included in the target row are not consecutive.

公开(公告)号：US20200159558A1

公开(公告)日：2020-05-21

申请号：US16423137

申请日：2019-05-27

申请人： Microsoft Technology Licensing, LLC

发明人： Yevgeniy BAK ,  Mehmet IYIGUN ,  Arun U. KISHAN

IPC分类号： G06F9/455 ,  G06F12/1045 ,  G06F12/109

摘要： To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

公开(公告)号：US10649912B2

公开(公告)日：2020-05-12

申请号：US15650365

申请日：2017-07-14

申请人： International Business Machines Corporation

发明人： Michael Johannes Jaspers ,  Markus Kaltenbach ,  Girish G. Kurup ,  Ulrich Mayer

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/1045 ,  G06F12/1027

摘要： The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein multiple translation engines are used to perform translations on request of one of a plurality of dedicated processor units. The method comprises: maintaining by a cache unit a dependency matrix for the engines to track for each processing unit if an engine is assigned to the each processing unit for a table walk. The cache unit may block a processing unit from allocating an engine to a translation request when the engine is already assigned to the processing unit in the dependency matrix.

公开(公告)号：US10599584B2

公开(公告)日：2020-03-24

申请号：US15806237

申请日：2017-11-07

申请人： Arm Limited

发明人： Andreas Due Engh-Halstvedt ,  Frank Langtind ,  Shareef Justin Jalloq

IPC分类号： G06F12/10 ,  G06F12/1045 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/0875 ,  G06F12/126 ,  G06F12/0895

摘要： When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.

公开(公告)号：US20200089622A1

公开(公告)日：2020-03-19

申请号：US16694751

申请日：2019-11-25

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung Ong

IPC分类号： G06F12/1045 ,  G06F15/78

摘要： A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

公开(公告)号：US10592424B2

公开(公告)日：2020-03-17

申请号：US15819378

申请日：2017-11-21

申请人： Arm Limited

发明人： Jonathan Curtis Beard ,  Stephan Diestelhorst

IPC分类号： G06F12/1009 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/1045 ,  G06F12/109

摘要： A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.

公开(公告)号：US10585806B2

公开(公告)日：2020-03-10

申请号：US16113561

申请日：2018-08-27

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Michael J. Moretti

IPC分类号： G06F12/00 ,  G06F12/1045 ,  G06F16/00 ,  G06F9/50 ,  G06F9/455 ,  G06F12/0864

摘要： Systems, methods, and software described herein provide accelerated input and output of data in a work process. In one example, a method of operating a support process within a computing system for providing accelerated input and output for a work process includes monitoring for a file mapping attempt initiated by the work process. The method further includes, in response to the file mapping attempt, identifying a first region in memory already allocated to a cache service, and associating the first region in memory with the work process.

公开(公告)号：US20200073795A1

公开(公告)日：2020-03-05

申请号：US16433148

申请日：2019-06-06

申请人： Toshiba Memory Corporation

发明人： Shigehiro Asano

IPC分类号： G06F12/02 ,  G11C11/56 ,  G11C16/16 ,  G11C16/08 ,  G11C16/30 ,  G06F3/06 ,  G06F12/1045 ,  G06F12/1009

摘要： According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller selects, as a write mode, at least one of a first mode in which N-bit data is written per memory cell in the nonvolatile memory and a second mode in which M-bit data is written per memory cell in the nonvolatile memory as a write mode. N is equal to or larger than one. M is larger than N. The controller selects the second mode when a reception speed of data, which is received in accordance with acceptance of one or more write commands from the host, is equal to or slower than a threshold, and selects the first mode when the reception speed is faster than the threshold.