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101.发明授权Method of testing universal flash storage (UFS) interface and memory device implementing method of testing UFS interface 有权通用闪存存储（UFS）接口和内存设备实现UFS接口测试方法的测试方法公开(公告)号：US09026854B2
公开(公告)日：2015-05-05
申请号：US13647415
申请日：2012-10-09
发明人： Ha-Neul Jeong , Woo-Seong Cheong
CPC分类号： G11C29/022 , G06F11/221 , G11C2029/5602
摘要： A method is provided for performing a self-test on a memory device in a test mode, where the memory device includes a universal flash storage (UFS) link layer and a UFS physical layer having a transmitting unit and a receiving unit. The method includes generating a first signal; sending the first signal from a test unit through the UFS link layer to the transmitting unit in the UFS physical layer to be transmitted to the receiving unit; receiving a second signal at the test unit from the receiving unit in the UFS physical layer through the UFS link layer, the second signal being the first signal received by the receiving unit; and testing an operation performed by at least one of the UFS physical layer and the UFS link layer based on the first signal and the second signal.
摘要翻译： 提供了一种用于在测试模式下对存储器件执行自检的方法，其中存储器件包括通用闪存存储（UFS）链路层和具有发送单元和接收单元的UFS物理层。 该方法包括产生第一信号; 将来自测试单元的第一信号通过UFS链路层发送到UFS物理层中的发送单元以发送到接收单元; 通过UFS链路层从UFS物理层的接收单元在测试单元处接收第二信号，第二信号是由接收单元接收的第一信号; 以及基于所述第一信号和所述第二信号来测试由所述UFS物理层和所述UFS链路层中的至少一个执行的操作。
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公开(公告)号：US09015545B2
公开(公告)日：2015-04-21
申请号：US13921753
申请日：2013-06-19
申请人： Unitest Inc
发明人： Eui Won Lee , Hyo Jin Oh
CPC分类号： G11C29/10 , G06F11/2221 , G06F13/385 , G06F13/4022 , G06F2213/0026 , G06F2213/0028 , G06F2213/0032 , G11C29/56008 , G11C2029/0401
摘要： Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.
摘要翻译： 公开了一种固态驱动测试仪，其将生成和比较测试图形数据和帧信息结构（FIS）数据的功能彼此分开，以将功能实现为单独的逻辑，从而通过减少负载来降低整个测试时间 的处理器。 固态驱动测试器包括用于接收用户测试存储器的测试条件的主机终端和产生与测试条件对应的测试模式的测试控制单元，以及根据存储器的接口类型自适应地选择接口 被测试以使用测试模式测试存储器，其中测试控制单元被分成用于控制存储器测试的控制模块和用于在硬件中实际执行测试的测试执行模块以实际测试多个存储器 时间。
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公开(公告)号：US09009549B2
公开(公告)日：2015-04-14
申请号：US13885779
申请日：2011-02-18
申请人： Ryoya Ichioka
发明人： Ryoya Ichioka
摘要： A RAM to be diagnosed is divided into n (n being an integer of 3 or greater) pieces of base regions. In an idle time of periodic processing performed in a system in which the RAM is incorporated, two base regions are selected from the divided base regions, and the selected two base regions are diagnosed using a diagnostic method capable of detecting a coupling fault. Thereafter, in an idle time of the periodic processing, operations to select an unselected pair of base regions and diagnose the selected pair are repeated, so as to diagnose all combinations of pairs.
摘要翻译： 待诊断的RAM被划分为n（n为3以上的整数）个基区。 在其中并入RAM的系统中执行的周期性处理的空闲时间中，从划分的基区选择两个基区，并且使用能够检测耦合故障的诊断方法诊断所选择的两个基区。 此后，在周期性处理的空闲时间中，重复选择未选择的基本区域对和诊断所选择的对的操作，以便诊断对的所有组合。
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104.发明授权公开(公告)号：US08954803B2
公开(公告)日：2015-02-10
申请号：US13030358
申请日：2011-02-18
申请人： Rajesh Chopra
发明人： Rajesh Chopra
IPC分类号： G06F11/00 , G06F11/263 , G06F11/27 , G11C29/56
CPC分类号： G06F11/263 , G06F11/27 , G11C29/56 , G11C29/56004
摘要： A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters. The PCDTE may transmit information off of the chip to exercise transmit/receive circuitry of the chip.
摘要翻译： 集成电路芯片上的可编程特征调试测试引擎（PCDTE）。 PCDTE包括接收并存储提供在芯片接口上的指令的指令存储器，以及接收并存储在芯片接口上提供的配置值的配置存储器。 PCDTE还包括响应于配置值配置多个地址计数器和数据寄存器的控制器。 控制器还执行指令，其中响应于指令从计数器检索读/写地址和写数据。 检索到的读/写地址和写数据用于访问被测内存。 可以同时访问被测存储器的多个端口。 可以链接多个指令。 指令可以指定计数器内的特殊计数功能和/或指定集成（链接）计数器。 PCDTE可以从芯片传送信息来锻炼芯片的发射/接收电路。
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公开(公告)号：US20140365837A1
公开(公告)日：2014-12-11
申请号：US14297858
申请日：2014-06-06
发明人： GUANG-JIAN WANG
CPC分类号： G11C29/56012 , G06F11/2242 , G11C29/56
摘要： A test apparatus and method for testing a server are provided. The server includes a CPU group and a memory module. The test apparatus is electrically coupled to the CPU group and the memory module. The CPU group includes a number of CPUs, where each CPU is coupled to other CPUs through a plurality of QPI buses. The test apparatus includes a first copying control unit, a second copying control unit and a calculation unit. The first copying control unit controls each CPU to copy data stored in the memory module to a cache of the CPU and records the copying time duration. The second copying control unit controls each CPU to copy data stored in the memory module to caches of other CPUs and records the copying time duration. The calculation unit obtains copying speed according to the copying time duration.
摘要翻译： 提供了一种用于测试服务器的测试设备和方法。 服务器包括一个CPU组和一个内存模块。 测试装置电耦合到CPU组和存储器模块。 CPU组包括多个CPU，其中每个CPU通过多个QPI总线耦合到其他CPU。 测试装置包括第一复印控制单元，第二复印控制单元和计算单元。 第一复制控制单元控制每个CPU将存储在存储器模块中的数据复制到CPU的高速缓存，并记录复制持续时间。 第二复制控制单元控制每个CPU将存储在存储器模块中的数据复制到其他CPU的高速缓存并记录复制持续时间。 计算单元根据复印持续时间获得复印速度。
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公开(公告)号：US08910001B2
公开(公告)日：2014-12-09
申请号：US13635004
申请日：2011-03-16
CPC分类号： G11C29/12 , G11C29/10 , G11C29/16 , G11C29/56 , G11C2029/3602
摘要： Method for testing a memory under test (1) including a plurality of memory cells and a Memory Built-In Self-Test Engine (2) connectable to a memory under test. The MBIST engine (2) is arranged to generate appropriate addressing and read and/or write operations to the memory under test (1). The MBIST engine (2) is connected to a March Element Stress register (MESR) (3), a generic march element register (GMER) (4), and a Command Memory (5). The GMER (4) specifies one of a set of Generic March Elements (GME), and the MESR (3) specifies the stress conditions to be applied. Only a few GMEs are required in order to specify most industrial algorithms. The architecture is orthogonal and modular, and all speed related information is contained in the GME. In addition, only little memory is required for the specification of the test, providing a low implementation cost, yet with a high flexibility.
摘要翻译： 用于测试包括多个存储器单元的测试存储器（1）的方法和可连接到被测存储器的存储器内置自检引擎（2）。 MBIST引擎（2）被布置成为被测试存储器（1）生成适当的寻址和读取和/或写入操作。 MBIST引擎（2）连接到March元素应力寄存器（MESR）（3），通用行进元素寄存器（GMER）（4）和命令存储器（5）。 GMER（4）指定了一组通用三角形元素（GME）中的一个，MESR（3）指定了要应用的应力条件。 为了指定大多数工业算法，只需要几个GME。 架构是正交和模块化的，所有速度相关信息都包含在GME中。 此外，测试规范只需要很少的内存，提供低的实施成本，但具有很高的灵活性。
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107.发明授权Apparatus and methods for testing writability and readability of memory cell arrays 有权用于测试记忆单元阵列的可编写性和可读性的装置和方法公开(公告)号：US08832508B2
公开(公告)日：2014-09-09
申请号：US12949574
申请日：2010-11-18
申请人： Carson Henrion , Michael Dreesen
发明人： Carson Henrion , Michael Dreesen
CPC分类号： G11C7/1069 , G11C7/1096 , G11C29/26 , G11C29/56 , G11C2029/0401 , G11C2029/2602
摘要： Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array.
摘要翻译： 提供了设备和方法，用于在访问存储器元件时同时选择存储器单元的多个阵列。 存储器元件包括耦合到第一位线节点的一个或多个存储器单元的第一阵列，耦合到第二位线节点的一个或多个存储器单元的第二阵列，用于访问第一阵列中的第一存储器单元的访问电路 耦合在第一位线节点和接入电路之间的第一晶体管，以及耦合在第二位线节点和接入电路之间的第二晶体管。 控制器耦合到第一晶体管和第二晶体管，并且控制器被配置为同时激活第一晶体管和第二晶体管以访问第一阵列中的第一存储单元。
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公开(公告)号：US08793540B2
公开(公告)日：2014-07-29
申请号：US13541670
申请日：2012-07-04
申请人： Takeshi Kawakami
发明人： Takeshi Kawakami
CPC分类号： G11C29/56004
摘要： Provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not.
摘要翻译： 提供了一种测试装置，包括：地址发生器，其生成被测存储器的地址; 选择器，在将地址提供给被测存储器之前，选择是否对地址生成器产生的地址执行位反转; 一个反转处理部分，如果选择器已经选择肯定地输出地址产生器对地址进行位反转后产生的地址，并且如果选择器具有地址，则输出由地址生成器生成的地址，而不对地址执行任何位反转 选择为负数; 以及供给部，其向被测试存储器提供经过反转处理部分输出的反转控制的地址和指示从反转处理部分输出的地址是否被反转的反相周期信号。
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公开(公告)号：US08782476B2
公开(公告)日：2014-07-15
申请号：US13338591
申请日：2011-12-28
申请人： Dae-Suk Kim
发明人： Dae-Suk Kim
摘要： A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.
摘要翻译： 输出具有第一和第二单元阵列的存储器的测试方法，通过压缩第一单元阵列的输出数据和第二单元阵列的输出数据而获得的第一压缩数据。 当第一压缩数据表示存在故障时，第一和第二单元阵列之一的输出数据被锁定为正常数据，并且通过压缩正常数据而获得的第二压缩数据并输出第一和第二单元中的另一个的数据 阵列被输出。
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110.发明授权公开(公告)号：US08745452B2
公开(公告)日：2014-06-03
申请号：US13587100
申请日：2012-08-16
申请人： Hyung Rok Oh , Chul Woo Park
发明人： Hyung Rok Oh , Chul Woo Park
CPC分类号： G11C13/0002 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C29/021 , G11C29/028 , G11C29/24 , G11C29/48 , G11C29/50 , G11C29/56 , G11C2029/5006
摘要： A resistive memory device and a system and method for testing the resistive memory device are provided. The resistive memory device includes a plurality of bit lines comprising at least one dummy bit line to which a plurality of resistive memory cells are connected, a conducting wire connected to the dummy bit line, a first switching element positioned between the dummy bit line and an external device outside the resistive memory device, and a second switching element positioned between the conducting wire and the external device. Accordingly, the operational reliability of the resistive memory device may be increased.
摘要翻译： 提供了一种电阻式存储器件以及用于测试电阻式存储器件的系统和方法。 电阻式存储器件包括多个位线，其包括连接多个电阻存储器单元的至少一个虚拟位线，连接到虚拟位线的导线，位于虚拟位线和第二开关元件之间的第一开关元件 位于电阻性存储器件外的外部器件，以及位于导线和外部器件之间的第二开关元件。 因此，可以增加电阻式存储器件的操作可靠性。
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