公开(公告)号：US20020167030A1

公开(公告)日：2002-11-14

申请号：US10176174

申请日：2002-06-21

发明人： Takashi Miida

IPC分类号： H01L027/148 ,  H01L029/768 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062

CPC分类号： H01L31/103 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14692

摘要： There is provided a solid state imaging device using a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. In configuration, in the solid state imaging device that comprises a photo diode formed in a second semiconductor layer 15a of opposite conductivity type in a first semiconductor layer 12 and 32 of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer 15b of opposite conductivity type in a third semiconductor layer 12 of one conductivity type adjacently to the photo diode, a carrier pocket 25 is provided in the fourth semiconductor layer 15b, and a portion of the first semiconductor layer 12, 32 under the second semiconductor layer 15a is thicker than a portion of the third semiconductor layer 12 under the fourth semiconductor layer 15b in a depth direction.

摘要翻译： 提供了一种使用在摄像机，电子照相机，图像输入照相机，扫描仪，传真机等中使用的阈值电压调制系统的MOS图像传感器的固态成像装置。 在配置中，在包括形成在第一半导体层12中的相反导电类型的第二半导体层15a和一种导电类型的32的第二半导体层15a中形成的光电二极管的固态成像器件以及形成在第一半导体层中的光信号检测绝缘栅场效应晶体管 在与光电二极管相邻的一种导电类型的第三半导体层12中具有相反导电类型的第四半导体层15b，在第四半导体层15b中设置载流子袋25，并将第一半导体层12,32的一部分 第二半导体层15a在第四半导体层15b的深度方向上比第三半导体层12的一部分厚。

公开(公告)号：US20020153540A1

公开(公告)日：2002-10-24

申请号：US10163353

申请日：2002-06-07

发明人： Sang-Il Jung ,  Jun-Taek Lee

IPC分类号： H01L021/00 ,  H01L027/148 ,  H01L029/768

CPC分类号： H01L27/14683 ,  H01L27/14806 ,  H01L27/14843

摘要： A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area. The discharge area includes a field insulating layer interposed between the insulating layer and the conductor extending from the barrier layer over the surface of the semiconductor substrate, and a discharge layer of the first conductivity type formed under the surface of the semiconductor substrate and adjacent the barrier layer of the barrier area over the surface layer. An impurity concentration of the discharge layer is greater than that of the first impurity layer.

公开(公告)号：US20020014639A1

公开(公告)日：2002-02-07

申请号：US09909878

申请日：2001-07-23

发明人： Hiroshi Imai ,  Hirokazu Itakura ,  Hiroyuki Ban

IPC分类号： H01L027/148 ,  H01L029/768

CPC分类号： H01L23/34 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has plural output circuits. Each of the plural output circuits has a semiconductor switching element and a heat protection circuit including a diode. When the heat protection circuit in a predetermined output circuit detects that heat emitted from the semiconductor switching element in the predetermined output circuit, the heat protection circuit turns off the semiconductor switching element in the predetermined output circuit. The plural output circuits are thermally isolated from each other by a trench and an insulation film. The trench and the insulation film prevent the heat from being transmitted from the predetermined output circuit to an adjacent output circuit. Therefore, even if the heat, by which the semiconductor switching element in the predetermined output circuit is turned off, is generated at the predetermined output circuit, the semiconductor switching element in the adjacent output circuit is not turned off by the heat.

摘要翻译： 半导体器件具有多个输出电路。 多个输出电路中的每一个具有半导体开关元件和包括二极管的热保护电路。 当预定输出电路中的热保护电路检测到来自预定输出电路中的半导体开关元件的热量时，热保护电路将预定输出电路中的半导体开关元件断开。 多个输出电路通过沟槽和绝缘膜彼此热隔离。 沟槽和绝缘膜防止热量从预定输出电路传输到相邻的输出电路。 因此，即使在预定的输出电路中产生预定的输出电路中的半导体开关元件被关断的热量，相邻的输出电路的半导体开关元件也不会被热断开。

公开(公告)号：US20020005531A1

公开(公告)日：2002-01-17

申请号：US09940990

申请日：2001-08-27

发明人： Jeffrey M. Levy

IPC分类号： H01L021/00 ,  H01L027/148 ,  H01L029/768 ,  H01L021/302 ,  H01L021/461

CPC分类号： H01L27/14601 ,  H01L31/02327

摘要： An anti-reflective layer is formed on the sidewalls of metal interconnects in an integrated circuit containing photodetector devices. After fabricating the photodetector devices, the metal interconnects are formed. An anti-reflective layer is formed over the interconnects and is directionally etched so that a portion of the anti-reflective layer remains covering the interconnect sidewalls, thereby reducing optical cross-talk in the photodetector devices due to sidewall reflection.

摘要翻译： 在包含光检测器件的集成电路中的金属互连的侧壁上形成抗反射层。 在制造光检测器件之后，形成金属互连。 在互连上形成抗反射层，并且被定向蚀刻，使得抗反射层的一部分保持覆盖互连侧壁，由此由于侧壁反射而减少光电探测器件中的光串扰。

公开(公告)号：US20010054722A1

公开(公告)日：2001-12-27

申请号：US09790597

申请日：2001-02-22

发明人： Jan Theodoor Jozef Bosiers

IPC分类号： H01L029/768 ,  H01L031/0376

CPC分类号： H01L29/76816 ,  H01L27/14806

摘要： In general, the output of a buried channel CCD is provided with a floating diffusion (4), which forms a storage site to determine the size of an electric charge. For this purpose, the floating diffusion may be connected to the input of an amplifier, such as a source follower (8). The charge is transferred to the floating zone from below an output gate OG to which a DC voltage is applied. To obtain a high sensitivity, i.e. a high voltage per electron, it is important to keep the capacitance of the floating zone as small as possible. The capacitance can be reduced by narrowing the channel at the output. This method of reducing C, however, is limited in known structures because this shape of the channel may induce an electric field in the channel which counteracts the transfer to the floating zone. To suppress this effect, the gate oxide (5) below the output gate is provided with a thicker part (5b) adjoining the floating diffusion (4). By virtue thereof, an additional field is induced below the output gate, which enhances the transfer of charge to the floating zone. This enables the channel to be narrowed, resulting in a low floating-zone capacitance, without decreasing the transfer efficiency. Said capacitance is reduced further by the thick oxide, which leads to a small capacitance between the floating zone and the output gate.

摘要翻译： 通常，掩埋通道CCD的输出具有浮动扩散（4），其形成存储位置以确定电荷的大小。 为此，浮动扩散可以连接到诸如源极跟随器（8）的放大器的输入。 从施加有直流电压的输出栅极OG的下方将电荷转移到浮动区域。 为了获得高灵敏度，即每个电子的高电压，重要的是保持浮动区域的电容尽可能小。 可以通过使输出端的通道变窄来减小电容。 然而，这种减小C的方法在已知的结构中是有限的，因为该通道的形状可以在通道中引起抵消到浮动区的传递的电场。 为了抑制这种效果，输出门下方的栅极氧化物（5）设置有与浮动扩散（4）相邻的较厚部分（5b）。 由此，在输出门下方引入附加场，这增强了电荷向浮动区的转移。 这使得通道变窄，导致低浮动电容，而不降低传输效率。 所述电容被厚氧化物进一步减小，这导致浮动区和输出栅之间的小电容。

公开(公告)号：US20010048122A1

公开(公告)日：2001-12-06

申请号：US09793833

申请日：2001-02-27

发明人： Gen Tada ,  Akio Kitamura ,  Masaru Saito ,  Naoto Fujishima

IPC分类号： H01L027/148 ,  H01L029/768

CPC分类号： H01L29/7816 ,  H01L29/402 ,  H01L29/405 ,  H01L29/7818 ,  H01L29/7835

摘要： The invention provides a semiconductor device, manufactured with low manufacturing costs, that prevents the breakdown voltage from lowering. The semiconductor device according to the invention includes a p-type highly resistive semiconductor substrate; an n-type offset region in the surface portion of the substrate; a p-type base region in the surface portion of the substrate, the base region including an nnull-type source region in the surface portion thereof, the base region including a channel portion in the extended portion thereof extended between the source region and the n-type offset region; a p-type offset region in the surface portion of the n-type offset region, the potential of the p-type offset region being fixed at the source potential; an nnull-type drain region in the surface portion of the n-type offset region; a field oxide film on the p-type offset region; a gate oxide film on the channel portion of the base region; a gate electrode on the gate oxide film; a source electrode on source region; a drain electrode on the drain region; an interlayer film; a protection film; and a spiral polysilicon thin film on the field oxide film, one end of the thin film being connected to the drain electrode, another end of the thin film being connected to the source electrode, the thin film being formed of pn-diodes connected in series.

摘要翻译： 本发明提供一种以低制造成本制造的半导体器件，其防止击穿电压降低。 根据本发明的半导体器件包括p型高电阻半导体衬底; 在衬底的表面部分中的n型偏移区域; 在基板的表面部分中的p型基极区域，所述基极区域在其表面部分包括n +型源极区域，所述基极区域包括在其延伸部分中的沟道部分在源区域和n 型偏移区域; 在n型偏移区域的表面部分中的p型偏移区域，p型偏移区域的电位固定在源极电位; n型偏移区域的表面部分中的n +型漏极区域; p型偏移区上的场氧化膜; 在所述基极区域的沟道部分上的栅氧化膜; 栅氧化膜上的栅电极; 源区上的源电极; 漏极区域上的漏电极; 中间膜; 保护膜; 以及场氧化膜上的螺旋状多晶硅薄膜，薄膜的一端与漏电极连接，薄膜的另一端与源电极连接，薄膜由串联连接的pn二极管形成 。

公开(公告)号：US20010046016A1

公开(公告)日：2001-11-29

申请号：US09910808

申请日：2001-07-24

发明人： Woon-Yong Park ,  Jong-Soo Yoon

IPC分类号： G02F001/1343 ,  G02F001/1345 ,  H01L021/00 ,  H01L021/84 ,  H01L029/04 ,  H01L031/036 ,  H01L027/148 ,  H01L029/768 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L27/124 ,  G03F1/50 ,  H01L21/0274 ,  H01L21/32139 ,  H01L27/1288

摘要： The present invention relates to the formation, on a substrate having a display area and a peripheral area, of a gate wire including a plurality of gate lines and gate electrodes in a display area and gate pads in the peripheral area, and of a common wire, including a common signal line and a plurality of common electrodes in the display area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact layer are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area, and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittances between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on position. At this time, a thin portion and a thick portion of the photoresist pattern are provided for the display area, and a thick portion and a zero thickness portion for the peripheral area. In the peripheral area, the portions of the passivation layer, the semiconductor layer, and the gate insulating layer on the gate pads, and the portions of the passivation layer on the data pads and under the zero thickness portion are removed. In the display area, the thin portion of the photoresist pattern, and the portions of the passivation layer and the semiconductor layer thereunder are removed, but the portions of the passivation layer under the thick portions of the photoresist pattern are not removed. Then, a plurality of pixel electrodes, redundant gate pads, and redundant data pads are formed.

公开(公告)号：US20010045580A1

公开(公告)日：2001-11-29

申请号：US09361700

申请日：1999-07-27

发明人： PIERRICK DESCURE

IPC分类号： H01L027/148 ,  H01L029/768

CPC分类号： H01L27/14685 ,  H01L27/14621

摘要： An array of photodiodes includes regions of a second conductivity type formed in a semiconductive region of a first conductivity type, divided into three interleaved sub-arrays. All the photodiodes of a same sub-array are coated with a same interference filter including at least one insulating layer of determined thickness coated with at least one conductive layer. According to the present invention, the conductive layers are electrically connected to the semiconductive region of a first conductivity type.

摘要翻译： 光电二极管阵列包括形成在第一导电类型的半导体区域中的第二导电类型的区域，被划分为三个交错的子阵列。 相同子阵列的所有光电二极管涂覆有相同的干涉滤光器，该干涉滤光器包括至少一个涂覆有至少一个导电层的确定厚度的绝缘层。 根据本发明，导电层电连接到第一导电类型的半导电区域。

公开(公告)号：US20010045577A1

公开(公告)日：2001-11-29

申请号：US09886110

申请日：2001-06-22

申请人： HAMAMATSU PHOTONICS K.K.

发明人： Hiroshi Akahori ,  Hisanori Suzuki ,  Kazuhisa Miyaguchi ,  Masaharu Muramatsu ,  Koei Yamamoto

IPC分类号： H01L027/148 ,  H01L029/768

CPC分类号： H01L27/14812

摘要： A semiconductor energy detector as disclosed herein is arranged so that an aluminum wiring pattern is formed on the front side of transfer electrodes of a CCD vertical shift register, which pattern includes meander-shaped auxiliary wirings for performing auxiliary application/supplement and additional wirings for performing auxiliary supplement of transfer voltages in a way independent of the auxiliary wirings with respective ones of such wirings being connected to corresponding transfer electrodes to thereby avoid a problem as to lead resistivities at those transfer electrodes made of polycrystalline silicon, thus achieving the intended charge transfer at high speeds with high efficiency.

摘要翻译： 这里所公开的一种半导体能量检测器被布置成在CCD垂直移位寄存器的传输电极的正面上形成铝布线图形，该垂直移位寄存器的图形包括用于执行辅助应用/补充的曲折辅助布线和用于执行的附加布线 以与辅助布线无关的方式辅助补偿传输电压，其中相应的这些布线连接到相应的传输电极，从而避免在由多晶硅制成的那些传输电极处的引线电阻的问题，从而实现预期的电荷转移 高速高效率。

公开(公告)号：US20010045576A1

公开(公告)日：2001-11-29

申请号：US09862425

申请日：2001-05-23

发明人： Sang-Il Jung ,  Jun-Taek Lee

IPC分类号： H01L021/00 ,  H01L021/339 ,  H01L027/148 ,  H01L029/768

CPC分类号： H01L27/14683 ,  H01L27/14806 ,  H01L27/14843

摘要： A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area. The discharge area includes a field insulating layer interposed between the insulating layer and the conductor extending from the barrier layer over the surface of the semiconductor substrate, and a discharge layer of the first conductivity type formed under the surface of the semiconductor substrate and adjacent the barrier layer of the barrier area over the surface layer. An impurity concentration of the discharge layer is greater than that of the first impurity layer.

摘要翻译： 屏障区域位于水平传送区域附近并且与场绝缘区域间隔开。 阻挡区域包括绝缘层和从半导体衬底的表面上的水平转印层延伸的导体，形成在半导体衬底的表面下方并且与第一导电性的第一杂质层相邻的第二导电类型的势垒层 水平传送区域的类型和从水平传送区域延伸并形成在阻挡层下面的第二杂质层。 放电区域位于屏障区域和场绝缘区域之间。 放电区域包括介于绝缘层和从半导体衬底的表面上的阻挡层延伸的导体之间的场绝缘层，以及形成在半导体衬底的表面下方并与屏障相邻的第一导电类型的放电层 层表面层上的屏障区域。 放电层的杂质浓度大于第一杂质层的杂质浓度。