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公开(公告)号：US20200243342A1
公开(公告)日：2020-07-30
申请号：US16646946
申请日：2018-08-14
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Jiale SU , Changfeng XIA , Guoping ZHOU , Xinwei ZHANG
IPC: H01L21/3065 , H01L21/02
Abstract: A method of forming a cavity based on a deep trench erosion, comprising: providing a semiconductor substrate (200), and performing the deep trench erosion to the semiconductor substrate to form an array of a plurality of trenches (201) in the semiconductor substrate (200), a pitch (D1) between the outermost grooves in the array being greater than a pitch (D2) between the remaining trenches in the array; and preforming an annealing treatment to the semiconductor substrate (200) to form a cavity (202) in the semiconductor substrate (200).
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公开(公告)号：US10707844B2
公开(公告)日：2020-07-07
申请号：US16312345
申请日：2017-06-21
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Xueyan Wang , Qiang Chen
Abstract: A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.
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公开(公告)号：US20200064152A1
公开(公告)日：2020-02-27
申请号：US16673634
申请日：2019-11-04
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Huagang WU
Abstract: A method for correcting the driving amplitude of a gyro sensor, mainly comprises adjusting the size of a driving signal (a preset amplitude value) through feedback of a sensor response amplitude signal (an average amplitude value) in a resonance maintaining time period, so that the response amplitude of the resonance maintaining time period tends to he equal, and a stable resonance amplitude is maintained. Also provided is a system for correcting the driving amplitude of a gyro sensor.
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公开(公告)号：US20200010316A1
公开(公告)日：2020-01-09
申请号：US16305119
申请日：2017-05-26
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Yonggang HU
Abstract: A MEMS microphone comprises a substrate (110), a lower electrode layer (120), a sacrificial layer (130), a stress layer (140), and an upper electrode layer (150). The substrate (110) is centrally provided with a first opening (111), and the lower electrode layer (120) stretches across the substrate (110). The sacrificial layer (130), the stress layer (140), and the upper electrode layer (150) are sequentially laminated on the lower electrode layer (120), and a second opening (160) is provided on the sacrificial layer (130) and the stress layer (140). The second opening (160) is provided in correspondence with the first opening (111). A stress direction of the stress layer (140) is reverse to a warpage direction of the substrate (110).
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公开(公告)号：US20200006529A1
公开(公告)日：2020-01-02
申请号：US16481576
申请日：2018-07-03
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Shukun QI , Guipeng SUN
IPC: H01L29/66 , H01L21/762 , H01L21/02 , H01L21/311
Abstract: Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; removing the nitrogen-containing compound side wall residue; and filling the first groove and the second groove with silicon oxide.
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Patent Agency Ranking
公开(公告)号：US10521546B2
公开(公告)日：2019-12-31
申请号：US15756799
申请日：2016-05-11
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Jinyin Wan , Jinheng Wang , Lei Zhang , Jie Chen
Abstract: An optical proximity correction method, comprising: dissecting an edge of a design pattern (120/220) to form a segment (Seg1/Seg2); setting target points of the segments (Seg1/Seg2), and if the segments (Seg1/Seg2) translate in a direction vertical to the segments (Seg1/Seg2), controlling tangent points (P1/P2) of the segments (Seg1/Seg2) tangent to a simulated pattern (110/210) to coincide with the target points; computing edge position differences of the target points; and correcting the design pattern (120/220) according to the edge position differences.
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公开(公告)号：US10079577B2
公开(公告)日：2018-09-18
申请号：US15565191
申请日：2016-01-29
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Xueyan Wang , Weiyan Zhang , Qiang Chen
CPC classification number: H03F1/26 , H03F3/387 , H03F3/45475 , H03F2200/165 , H03F2203/45514 , H03F2203/45551
Abstract: A signal amplification circuit comprises a low pass filter circuit (100). The low pass filter circuit (100) comprises two input ends and two output ends and further comprises two capacitors (C1, C2) having opposite polarities respectively connected between two output ends. A buffer circuit (200) comprises two input ends, a first operational amplifier (A1) and a second operational amplifier (A2), two output ends and a plurality of switches. A switched capacitor integrated circuit (300) comprises two input ends, a third operational amplifier (A3), a plurality of capacitor modules, a plurality of chopper modulators and two output ends. A signal switch (S) is used to control the on and off states of voltage signal before amplification.
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公开(公告)号：US20180175804A1
公开(公告)日：2018-06-21
申请号：US15565191
申请日：2016-01-29
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Xueyan WANG , Weiyan ZHANG , Qiang CHEN
CPC classification number: H03F1/26 , H03F3/45475 , H03F2200/165 , H03F2203/45514
Abstract: A signal amplification circuit comprises a low pass filter circuit (100). The low pass filter circuit (100) comprises two input ends and two output ends and further comprises two capacitors (C1, C2) having opposite polarities respectively connected between two output ends. A buffer circuit (200) comprises two input ends, a first operational amplifier (A1) and a second operational amplifier (A2), two output ends and a plurality of switches. A switched capacitor integrated circuit (300) comprises two input ends, a third operational amplifier (A3), a plurality of capacitor modules, a plurality of chopper modulators and two output ends. A signal switch (S) is used to control the on and off states of voltage signal before amplification.
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公开(公告)号：US20180033677A1
公开(公告)日：2018-02-01
申请号：US15547200
申请日：2015-09-24
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
IPC: H01L21/762
CPC classification number: H01L21/76202 , H01L21/762 , H01L21/76205 , H01L21/76224 , H01L21/76227 , H01L21/76264 , H01L21/76286 , H01L21/763 , H01L21/823481
Abstract: A method for preparing a trench isolation structure, which comprises the following steps of: providing a substrate; forming an oxide layer on the substrate; successively generating an oxidation barrier layer and an ethyl orthosilicate layer on the surface of the oxide layer; etching the oxidation barrier layer and the ethyl orthosilicate layer; corroding the substrate to form a trench by using the oxidation barrier layer and the ethyl orthosilicate layer as mask layers; removing the ethyl orthosilicate layer, and oxidizing a side wall of the trench by using the oxidation barrier layer as a barrier layer; filling the trench with a polysilicon and then etching back the polysilicon, and removing the polysilicon on the surface of the oxidation barrier layer; and removing the oxidation barrier layer and the oxide layer on the surface of the substrate.
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公开(公告)号：US20170192363A1
公开(公告)日：2017-07-06
申请号：US15315168
申请日：2015-06-26
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Zhenhai YAO
CPC classification number: G03F7/70633 , G03F1/00 , G03F1/38 , G03F7/70775 , G03F9/7003 , G03F9/7019 , G03F9/7046 , G03F9/7069
Abstract: A lithography stepper alignment and control method, comprising: providing a test template having a plurality of field sizes, and deriving a set of overlay values for each field size (S1); calculating a set of compensation amounts for the overlay value of each field size (S2); and, comparing alignment compensation values for a product with each compensation amount for each field size, selecting as the product alignment compensation values the set of compensation amounts of a field size closest to estimated alignment compensation values, and, using the product alignment compensation values to perform alignment compensation on said product (S3).
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