Apparatus and method for signal bus line layout in semiconductor device
    111.
    发明授权
    Apparatus and method for signal bus line layout in semiconductor device 失效
    半导体器件中信号总线布线的装置和方法

    公开(公告)号:US07566589B2

    公开(公告)日:2009-07-28

    申请号:US11809593

    申请日:2007-06-01

    Abstract: A device and method for layout and fabrication of power supply bus lines in an integrated circuit such as a memory circuit are described. In accordance with the present invention, power bus lines and bonding pads of the circuit are not necessarily formed in both edge regions and center regions of the device. The bonding pads are formed in the region according to the package being used, and the power bus lines are formed in the other region. This is accomplished by forming the bonding pads over landing pads. Landing pads are formed in both the center region and the edge region under the top surface of the device. If the device is to be packaged in an edge pad configuration, the bonding pads are formed over the landing pads in the edge region, and power supply bus lines can be formed over the landing pads in the center region. Similarly, if the device is to be packaged in a center pad configuration, the bonding pads are formed over the landing pads in the center region, and the power supply bus lines can be formed over the landing pads in the edge region.

    Abstract translation: 描述了诸如存储器电路的集成电路中的电源总线布线和制造的装置和方法。 根据本发明,电路的电源总线线路和接合焊盘不一定形成在器件的两个边缘区域和中心区域中。 接合焊盘形成在根据使用的封装的区域中,并且电力总线线路形成在另一区域中。 这通过在着陆垫上形成接合垫来实现。 着陆垫形成在装置的上表面下方的中心区域和边缘区域中。 如果将该器件封装在边缘焊盘配置中,则焊接区形成在边缘区域的着陆焊盘之上,并且电源总线可以形成在中心区域的着陆焊盘上。 类似地,如果要将器件封装在中心焊盘结构中,则接合焊盘形成在中心区域的着陆焊盘之上,并且电源总线可以形成在边缘区域的着陆焊盘上。

    GALLIUM NITRIDE/SAPPHIRE THIN FILM HAVING REDUCED BENDING DEFORMATION
    115.
    发明申请
    GALLIUM NITRIDE/SAPPHIRE THIN FILM HAVING REDUCED BENDING DEFORMATION 有权
    具有减少弯曲变形的氮化钠/ SAPPHIRE薄膜

    公开(公告)号:US20080248259A1

    公开(公告)日:2008-10-09

    申请号:US11869080

    申请日:2007-10-09

    Abstract: The present invention relates to a gallium nitride/sapphire thin film, wherein a curvature radius thereof is positioned on the right side of a curve plotted from the following functional formula (I): Y=Y0+A·e−(x1−1)/T1+B·(1−e−x2/T2)   (I) wherein Y is the curvature radius (m) of a gallium nitride/sapphire thin film, x1 is the thickness (μm) of a gallium nitride layer, x2 is the thickness (mm) of a sapphire substrate, Y0 is −107±2.5, A is 24.13±0.50, B is 141±4.5, T1 is 0.56±0.04, and T2 is 0.265±0.5.

    Abstract translation: 本发明涉及一种氮化镓/蓝宝石薄膜,其曲率半径位于从以下函数式(I)绘制的曲线的右侧:<?in-line-formula description =“In-line 公式“end =”lead“?> Y = Y <0> - (x -1)/ T 1 + B。(1-e / T 2 )(I)<?in-line-formula description =“In-line Formulas”end = “尾”→其中Y是氮化镓/蓝宝石薄膜的曲率半径(m),x 1是氮化镓层的厚度(mum),x 2 < / SUB>是蓝宝石衬底的厚度(mm),Y 0 <0>为-107±2.5,A为24.13±0.50,B为141±4.5,T 1 < 为0.56±0.04,T <2>为0.265±0.5。

    MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS
    117.
    发明申请
    MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS 有权
    具有处理器之间主机接口的多路可访问半导体存储器件

    公开(公告)号:US20080077937A1

    公开(公告)日:2008-03-27

    申请号:US11829859

    申请日:2007-07-27

    CPC classification number: G11C7/1075 G11C7/1012 G11C11/4096

    Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

    Abstract translation: 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列,该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元,用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元,以提供用于两个或多个处理器之间的通信的接口功能。

    Connector
    118.
    发明申请
    Connector 有权
    连接器

    公开(公告)号:US20080076286A1

    公开(公告)日:2008-03-27

    申请号:US11861579

    申请日:2007-09-26

    CPC classification number: H01R13/62911 H01R13/506 H01R13/62927

    Abstract: A connector includes a cap detachably coupled to a plug in a coupling direction. The cap and the plug electrically connect a current there between. A lever is coupled to the plug. The lever is moveable linearly in a direction the same as the coupling direction. A coupling is actuated by the linear movement of the lever. The coupling draws and compulsorily presses the cap into the plug in the coupling direction to couple the cap and the plug.

    Abstract translation: 连接器包括在联接方向上可拆卸地联接到插头的盖。 盖和插头电连接其间的电流。 杠杆连接到插头。 杠杆在与联接方向相同的方向上线性移动。 通过杠杆的线性运动来致动联轴器。 联轴器拉动并强制地将盖子按联接方向按压到插头中以联接盖子和插头。

    Liquid crystal display
    120.
    发明申请
    Liquid crystal display 失效
    液晶显示器

    公开(公告)号:US20070296903A1

    公开(公告)日:2007-12-27

    申请号:US11640308

    申请日:2006-12-18

    CPC classification number: G02F1/133608

    Abstract: A liquid crystal display device includes a liquid crystal display panel, a plurality of lamps for irradiating light onto the liquid crystal display panel, a cover bottom that houses the plurality of lamps, an inverter printed circuit board having a first surface and a second surface opposite to the first surface with an insulation base layer between the first and second surfaces, wherein the second surface is adjacent to the cover bottom, a transformer on the first surface of the inverter printed circuit board, and a metal shielding pattern on the second surface of the inverter printed circuit board directly between the transformer and the cover bottom.

    Abstract translation: 一种液晶显示装置,包括液晶显示面板,用于将光照射到液晶显示面板上的多个灯,容纳多个灯的盖底部,具有第一表面和第二表面的反相印刷电路板 在所述第一表面和所述第一表面和所述第二表面之间具有绝缘基底层,其中所述第二表面与所述盖底部相邻,所述逆变器印刷电路板的第一表面上的变压器和所述反相印刷电路板的第二表面上的金属屏蔽图案 逆变器印刷电路板直接在变压器和盖底之间。

Patent Agency Ranking