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公开(公告)号：US10891554B2
公开(公告)日：2021-01-12
申请号：US16258082
申请日：2019-01-25
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Paul I. Bunyk , Mohammad H. S. Amin , Emile M. Hoskinson
Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.
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公开(公告)号：US10885459B2
公开(公告)日：2021-01-05
申请号：US15962729
申请日：2018-04-25
Applicant: D-Wave Systems Inc.
Inventor： Jacob Daniel Biamonte , Andrew J. Berkley , Mohammad H.S. Amin
Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.
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公开(公告)号：US20200379768A1
公开(公告)日：2020-12-03
申请号：US16854396
申请日：2020-04-21
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew J. Berkley , Ilya V. Perminov , Mark W. Johnson , Christopher B. Rich , Fabio Altomare , Trevor M. Lanting
IPC: G06F9/38 , G06F16/901 , G06N10/00
Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.
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公开(公告)号：US20200372393A1
公开(公告)日：2020-11-26
申请号：US16988232
申请日：2020-08-07
Applicant: D-WAVE SYSTEMS INC.
Inventor： Robert B. Israel , Trevor M. Lanting , Andrew D. King
Abstract: Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.
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公开(公告)号：US20200266234A1
公开(公告)日：2020-08-20
申请号：US16389669
申请日：2019-04-19
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker
Abstract: Apparatus and methods advantageously provide parallel-plate capacitors in superconducting integrated circuits. A method may include forming a metal-oxide layer to overlie at least a portion of a first capacitor plate, the first capacitor plate comprising a superconductive material, and depositing a second capacitor plate to overlie at least a portion of the metal-oxide layer, the second capacitor plate comprising a superconductive material. The method may include depositing a base electrode of superconductive material to overlie at least a portion of a substrate, depositing the first capacitor plate to overlie at least a portion of the base electrode, and superconductingly electrically coupled to the base electrode, and depositing a counter electrode of superconductive material to overlie at least a portion of the second capacitor plate, the counter electrode superconductingly electrically coupled to the second capacitor plate. The superconducting integrated circuit may include a parallel-plate capacitor and a Josephson junction.
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Patent Agency Ranking
公开(公告)号：US10748079B2
公开(公告)日：2020-08-18
申请号：US16694693
申请日：2019-11-25
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号：US10700256B2
公开(公告)日：2020-06-30
申请号：US15679963
申请日：2017-08-17
Applicant: D-WAVE SYSTEMS INC.
Inventor： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
IPC: H01L39/24 , H01L27/18 , H01L39/22 , H01L21/285 , H01L39/02 , H01L39/12 , B82Y10/00 , H01L21/768 , G06N10/00
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
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公开(公告)号：US10691633B2
公开(公告)日：2020-06-23
申请号：US16421211
申请日：2019-05-23
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H. S. Amin , Geordie Rose , David Grant , Miles F. H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Methods and systems for solving various computational problems with quantum processors are provided. Such quantum processors comprise a plurality of quantum devices together with a plurality of coupling devices. The quantum processor is initialized by setting states of the quantum devices and coupling devices and allowed to evolve to a final state which approximates a natural ground state of the computational problem. The final state can include values of nodes arranged in a lattice in the quantum processor and can represent a solution to the computational processor. The computational problem can have complexity P, NP, NP-Hard, or NP-Complete and may be mapped to a quantum processor with nearest-neighbor and next-nearest-neighbor couplings. The solution to the computational problem can be read out from the quantum processor and transmitted as a data signal embodied in a carrier wave.
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119.发明申请公开(公告)号：US20200111016A1
公开(公告)日：2020-04-09
申请号：US16694693
申请日：2019-11-25
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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120.发明授权公开(公告)号：US10599988B2
公开(公告)日：2020-03-24
申请号：US15448361
申请日：2017-03-02
Applicant: D-Wave Systems Inc.
Inventor： Murray C. Thom , Aidan P. Roy , Fabian A. Chudak , Zhengbing Bian , William G. Macready , Robert B. Israel , Kelly T.R. Boothby , Sheir Yarkoni , Yanbo Xue , Dmytro Korenkevych
IPC: G06N10/00
Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
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