公开(公告)号：US06879703B2

公开(公告)日：2005-04-12

申请号：US10220776

申请日：2002-01-10

Applicant: Ching-Yung Lin ,  Shih-Fu Chang

Inventor： Ching-Yung Lin ,  Shih-Fu Chang

IPC: G06T1/00 ,  H04N1/32 ,  G06K9/10

CPC classification number: G06T1/0057 ,  G06T1/0042 ,  G06T1/005 ,  G06T2201/0052 ,  G06T2201/0061 ,  H04N1/32165 ,  H04N1/32187 ,  H04N1/32277 ,  H04N1/3232 ,  H04N2201/3236 ,  H04N2201/327

Abstract: Digital watermarks are embedded in image data (102)in order to enable authentication of the image data and/or replacement of rejected portions of the image data. Authentication codes are derived by comparing selected discrete cosine transform (DCT) (104) coefficients within DCT data (106) derived from the original, spatial-domain image data. The authentication codes thus generated are embedded in DCT coefficients (612) other than the ones which were used to derive the authentication codes. The resulting, watermarked data can be sent or made available to one or more recipients who can compress or otherwise use the watermarked data. Image data derived from the watermarked data—e.g, compressed versions of the watermarked data—can be authenticated by: extracting the embedded authentication codes, comparing DCT coefficients derived from the coefficients from which the original authentication codes were generated; and determining whether the compared DCT coefficients are consistent with the extracted authentication codes.

Abstract translation: 数字水印被嵌入在图像数据（102）中，以便能够对图像数据进行认证和/或替换图像数据的被拒绝的部分。 通过比较从原始的空间域图像数据导出的DCT数据（106）内的选定的离散余弦变换（DCT）（104）系数，导出认证码。 这样生成的认证码被嵌入除了用于导出认证码的那些之外的DCT系数（612）中。 所得到的水印数据可以被发送或使其可用于可压缩或以其他方式使用水印数据的一个或多个接收者。 从水印数据导出的图像数据（例如，水印数据的压缩版本）可以通过以下方式来认证：提取嵌入的认证码，比较从产生原始认证码的系数导出的DCT系数; 以及确定所述比较的DCT系数是否与所提取的认证码一致。

公开(公告)号：US06818491B2

公开(公告)日：2004-11-16

申请号：US10627834

申请日：2003-07-25

Applicant: Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

Inventor： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu ,  Mervyn Wong

IPC: H01L218238

CPC classification number: G11C16/3404 ,  G11C16/0416 ,  G11C16/344 ,  H01L27/115 ,  H01L29/66825

Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

Abstract translation: 在本发明中，示出了在NOR型EEPROM闪速存储器阵列的存储单元操作中使用三个并行字线电压的方法。 第一并行字线电压控制在所选择的存储器块内的选定字线上的操作。 第二并发字线电压抑制所选存储块中未选择的字线上的单元，并且第三并发字线电压抑制未被选择的块中的未选择的单元从干扰条件。 此外，三个连续的字线电压允许块被擦除，块内的页被擦除，并且块内的页被禁止进一步擦除。 三个连续的电压还允许检测电池的过度擦除，基于页面的校正，以及验证校正的单元的阈值电压是否高于擦除值但低于擦除值。 本文描述的方法产生具有窄电压分布的电池阈值电压。

公开(公告)号：US06788611B2

公开(公告)日：2004-09-07

申请号：US10423558

申请日：2003-04-25

Applicant: Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

Inventor： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

IPC: G11C800

CPC classification number: G11C16/10 ,  G11C7/18 ,  G11C8/12 ,  G11C2216/22

Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.

Abstract translation: 在本发明中公开了一种用于同时读和写操作的闪速存储器。 存储器被划分成多个扇区，每个扇区具有扇区解码器。 扇区解码器将多个主位线连接到包含在每个存储器扇区中的多个子位线A 2解码器用于演示本发明，尽管包括2解码器和分层式解码器的其他解码器可以 使用。 存储器阵列可以由各种架构进行配置，包括NOR，OR，NAND，AND，Dual-String和DINOR。 存储器单元可以由包括ETOX，FLOTOX，EPROM，EEPROM，分离栅极和PMOS的各种阵列结构形成。

公开(公告)号：US06574152B1

公开(公告)日：2003-06-03

申请号：US10104736

申请日：2002-03-22

Applicant: Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

Inventor： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC: G11C700

CPC classification number: G11C16/30 ,  G11C2207/105 ,  G11C2207/2227

Abstract: In the present invention an EEPROM flash memory is operated using the I/O pins of an EPROM. A novel circuit is used that allows a plurality of voltages to be applied at different times to a single pin designated as CEB (chip enable bar) that permits reading and writing of the flash memory chip. The plurality of voltages can range from a positive voltage, to a ground voltage and to a negative voltage. When a positive voltage like Vdd is applied to the the CEB pin the chip is disabled and entered into a standby mode. When a ground voltage is applied to the CEB pin, the flash memory chip is enabled and a read operation can be performed. When a high negative voltage is applied to the CEB pin, the circuit of the present invention produces an internal high negative voltage to be used for a write operation.

Abstract translation: 在本发明中，使用EPROM的I / O引脚来操作EEPROM闪速存储器。 使用一种新颖的电路，其允许在不同时间将多个电压施加到指定为允许读取和写入闪存芯片的CEB（芯片使能条）的单个引脚。 多个电压可以从正电压到接地电压和负电压的范围。 当Vdd等正电压施加到CEB引脚时，芯片被禁止并进入待机模式。 当接地电压施加到CEB引脚时，闪存芯片被使能，并且可以执行读操作。 当向CEB引脚施加高负电压时，本发明的电路产生用于写入操作的内部高负电压。

公开(公告)号：US06535974B1

公开(公告)日：2003-03-18

申请号：US09336411

申请日：1999-06-18

Applicant: Yung-Fu Chang ,  Randal A. Leeson

Inventor： Yung-Fu Chang ,  Randal A. Leeson

IPC: G06F300

CPC classification number: G06F9/4406 ,  G06F1/24

Abstract: A device (10) for user replacement of an inoperable, first boot loader program includes a boot memory (20) including the first boot loader program beginning at a first address, a PCMCIA card (15) including a second boot loader program beginning at a second memory address, and a selector switch (12). Selector switch (12) receives the user selection of one of the first boot loader program and the second boot loader program, and generates a selection signal corresponding to the user selected boot loader program. Combinational logic (21) receiving the selection signal, enables the selected boot loader program and disabling the other boot loader program.

Abstract translation: 用于替换不可操作的第一引导加载程序的设备（10）包括引导存储器（20），其包括从第一地址开始的第一引导加载程序，PCMCIA卡（15），其包括从 第二存储器地址和选择器开关（12）。 选择器开关（12）接收第一引导加载程序和第二引导加载程序之一的用户选择，并且生成与用户选择的启动加载程序相对应的选择信号。 接收选择信号的组合逻辑（21）启用所选择的启动加载程序并禁用其他启动加载程序。

公开(公告)号：US06493929B2

公开(公告)日：2002-12-17

申请号：US09851115

申请日：2001-05-09

Applicant: Michael Holland ,  Chi-Fu Chang

Inventor： Michael Holland ,  Chi-Fu Chang

IPC: H01R43042

CPC classification number: B25B27/10 ,  H01R9/0518 ,  H01R43/042 ,  Y10T29/53222 ,  Y10T29/53261 ,  Y10T29/53952

Abstract: The present invention relates to a guide tool, the said guide tool is capable of assisting one end of a coaxial cable to be coupled to an end connector; it comprises of a body installed with a guide mechanism therein, the said guide mechanism possesses a guide tube for guiding the cable central conductors of different regulations; the said guide tube can move along the direction of the axle line by the elastic element for rapidly and precisely inserting the central conductor and the dielectric into the columnar member of the end connector and further becomes the best auxiliary tool.

Abstract translation: 导向工具本发明涉及一种导向工具，所述导向工具能够协助同轴电缆的一端连接到端部连接器; 它包括在其中安装有导向机构的主体，所述引导机构具有用于引导不同规定的电缆中心导体的导管; 所述引导管可以通过弹性元件沿着轴线的方向移动，用于将中心导体和电介质快速且精确地插入到端部连接器的柱状构件中，并且进一步成为最佳的辅助工具。

公开(公告)号：US06327821B1

公开(公告)日：2001-12-11

申请号：US09550314

申请日：2000-04-14

Applicant: Wen Fu Chang

Inventor： Wen Fu Chang

IPC: E04C202

CPC classification number: E05G1/024 ,  E04B1/94

Abstract: A fire-proof refuge shelter includes a plurality of partition walls joined together by bolts and screws to form a closed box provided with a pair of sliding doors, characterized in that: each of the partition walls being made of a surface layer, an intermediate heat-resistant layer and an inner heat-resistant cement layer, the surface layer being made of fire-proof glass fiber or calcium silicate or mineral fiber, the inner heat resistant layer being a fire-proof sound absorbing board made of lightweight bone concrete or made by solidation of heat resistant concrete, and the intermediate heat resistant sand layer being made of non-combustible clay, silicon stone or substance primarily consisting of carbon, whereby oxygen tanks, flashlights and so on are arranged inside the shelter for people who waits for rescue.

Abstract translation: 防火避难所包括通过螺栓和螺钉连接在一起的多个分隔壁，以形成设置有一对滑动门的封闭箱，其特征在于：每个分隔壁由表面层，中间热 表面层由防火玻璃纤维或硅酸钙或矿物纤维制成，内层耐热层是由轻质骨混凝土制成的防火吸音板，或制成 通过耐热混凝土的固化，中间耐热砂层由不可燃粘土，硅石或主要由碳组成的物质制成，其中氧气罐，手电筒等安排在等待救援的人的避难所内 。

公开(公告)号：US06262622B1

公开(公告)日：2001-07-17

申请号：US09479649

申请日：2000-01-08

Applicant: Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen

Inventor： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen

IPC: G05F302

CPC classification number: G05F3/242

Abstract: A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.

Abstract translation: 高压输入电路包括三阱NMOS，用于减小跨越其漏极结的电压应力，以防止其击穿。 三阱NMOS在P衬底中形成在深N阱中的P阱中制造。 P阱通过P阱电压控制装置耦合到电源电压，以减少跨越漏极结的电压差。 低电压信号输入电路部分也被添加到高电压输入电路，以允许高电压输入引脚接收其它信号并减少集成电路的总引脚数。 在低电压信号输入电路中使用诸如NAND门而不是反相器的双输入缓冲器，用于降低对低电压信号输入电路中的器件的电压应力。

公开(公告)号：US6134150A

公开(公告)日：2000-10-17

申请号：US360315

申请日：1999-07-23

Applicant: Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Vei-Han Chan ,  Hung-Sheng Chen

Inventor： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Vei-Han Chan ,  Hung-Sheng Chen

IPC: G11C16/14 ,  G11C7/00

CPC classification number: G11C16/14

Abstract: In the present invention a flash memory configuration is disclosed that eliminates the need for one of two pump circuits that are commonly required to support an erase function of memory cells on a flash memory chip. The flash memory cells are placed into a triple well structure with a P-well contained within a deep N-well that resides on a P-substrate. The bias voltages for erase of the flash memory cells are chosen so as to require only one voltage pump circuit to be included in the flash memory chip. The chip bias, V.sub.DD, is used for the source of the memory cells and a negative gate voltage is raised in magnitude to maintain the efficiency of the erase operation. The P-well is biased with a negative voltage that is sufficient to prevent the high negative voltage connected to the gate from causing breakdown in word line decoder circuits. The deep N-well and the P-substrate are biased such as to back bias the P/N junctions between the triple well structure.

Abstract translation: 在本发明中，公开了一种闪存配置，其不需要通常需要两个泵电路之一来支持闪存芯片上的存储器单元的擦除功能。 将闪存单元置于三阱结构中，其中P阱包含在驻留在P基底上的深N阱内。 选择用于擦除闪存单元的偏置电压，以便仅需要将一个电压泵电路包括在闪存芯片中。 芯片偏置VDD用于存储单元的源极，负栅极电压上升幅度以保持擦除操作的效率。 P阱被施加负电压，该负电压足以防止连接到栅极的高负电压引起字线解码器电路中的击穿。 深N阱和P衬底被偏置，以便反向偏置三阱结构之间的P / N结。

公开(公告)号：US6058113A

公开(公告)日：2000-05-02

申请号：US940251

申请日：1997-09-30

Applicant: Young-fu Chang

Inventor： Young-fu Chang

IPC: H04L12/18 ,  H04L12/56 ,  H04L12/28

CPC classification number: H04L12/5695 ,  H04L12/185 ,  H04L47/724 ,  H04L47/745 ,  H04L47/746 ,  H04L47/805 ,  H04L47/806 ,  H04L2012/5631 ,  H04L2012/5642

Abstract: A method for establishing and maintaining data communication between communication devices including at least one sender communication device and a receiving communication device of a multicast group which are interconnected by a communications network of switching nodes that involves determining when there is a change in the state of the multicast group. The receiving communication device normally maintains a resource reservation in response to data being substantially continuously received at the switching nodes unless there is a change in the state of the multicast group. Upon determination of the state change in the multicast group, the inventive method changes the resource reservation even while data is being continually received at the switching nodes.

Abstract translation: 一种用于建立和维护通信设备之间的数据通信的方法，所述通信设备包括由交换节点的通信网络互连的多播组的至少一个发送者通信设备和接收通信设备，所述交换节点涉及确定何时发生 组播组。 接收通信设备通常维护资源预留，以响应于在交换节点处基本上连续接收的数据，除非多播组的状态发生变化。 一旦确定了多播组中的状态变化，本发明的方法即使在交换节点处连续地接收数据的同时也改变资源预留。