公开(公告)号：US06262622B1

公开(公告)日：2001-07-17

申请号：US09479649

申请日：2000-01-08

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen

IPC分类号： G05F302

CPC分类号： G05F3/242

摘要： A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.

摘要翻译： 高压输入电路包括三阱NMOS，用于减小跨越其漏极结的电压应力，以防止其击穿。 三阱NMOS在P衬底中形成在深N阱中的P阱中制造。 P阱通过P阱电压控制装置耦合到电源电压，以减少跨越漏极结的电压差。 低电压信号输入电路部分也被添加到高电压输入电路，以允许高电压输入引脚接收其它信号并减少集成电路的总引脚数。 在低电压信号输入电路中使用诸如NAND门而不是反相器的双输入缓冲器，用于降低对低电压信号输入电路中的器件的电压应力。

公开(公告)号：US06660585B1

公开(公告)日：2003-12-09

申请号：US09531787

申请日：2000-03-21

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Vei-Han Chan ,  Hung-Sheng Chen ,  Fu-Chang Hsu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  G11C16/0416 ,  H01L21/28273

摘要： In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.

摘要翻译： 在本发明中，公开了一种堆叠栅极闪存单元，其在器件的漏极侧具有轻掺杂漏极（LDD），并且使用源使用热电子发生进行编程并使用Fowler-Nordheim隧道擦除浮动栅极。 通过利用LDD和使用源进行编程和擦除的单元的偏置来减少干扰条件。 作为减少热电子产生的LDD的结果，漏极的电场大大减小。 LDD还有助于在编程期间减少位线干扰条件。 通过将未选择的单元的位线预处理为Vcc，使未选择的单元中的瞬态位线干扰条件最小化。

公开(公告)号：US6134150A

公开(公告)日：2000-10-17

申请号：US360315

申请日：1999-07-23

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Vei-Han Chan ,  Hung-Sheng Chen

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee ,  Vei-Han Chan ,  Hung-Sheng Chen

IPC分类号： G11C16/14 ,  G11C7/00

CPC分类号： G11C16/14

摘要： In the present invention a flash memory configuration is disclosed that eliminates the need for one of two pump circuits that are commonly required to support an erase function of memory cells on a flash memory chip. The flash memory cells are placed into a triple well structure with a P-well contained within a deep N-well that resides on a P-substrate. The bias voltages for erase of the flash memory cells are chosen so as to require only one voltage pump circuit to be included in the flash memory chip. The chip bias, V.sub.DD, is used for the source of the memory cells and a negative gate voltage is raised in magnitude to maintain the efficiency of the erase operation. The P-well is biased with a negative voltage that is sufficient to prevent the high negative voltage connected to the gate from causing breakdown in word line decoder circuits. The deep N-well and the P-substrate are biased such as to back bias the P/N junctions between the triple well structure.

摘要翻译： 在本发明中，公开了一种闪存配置，其不需要通常需要两个泵电路之一来支持闪存芯片上的存储器单元的擦除功能。 将闪存单元置于三阱结构中，其中P阱包含在驻留在P基底上的深N阱内。 选择用于擦除闪存单元的偏置电压，以便仅需要将一个电压泵电路包括在闪存芯片中。 芯片偏置VDD用于存储单元的源极，负栅极电压上升幅度以保持擦除操作的效率。 P阱被施加负电压，该负电压足以防止连接到栅极的高负电压引起字线解码器电路中的击穿。 深N阱和P衬底被偏置，以便反向偏置三阱结构之间的P / N结。

公开(公告)号：US06891221B2

公开(公告)日：2005-05-10

申请号：US10790578

申请日：2004-03-01

申请人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

发明人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/115

摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

摘要翻译： 在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。 单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。 位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。 由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。 使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。 通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。

公开(公告)号：US06717846B1

公开(公告)日：2004-04-06

申请号：US09696085

申请日：2000-10-26

申请人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

发明人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

IPC分类号： G11C1616

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/115

摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. The cells are crased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

摘要翻译： 在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。 单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。 位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。 由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。 使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。 使用Fowler-Nordheim，通过在浮栅的壁上形成的多晶硅氧化物，利用Fowler-Nordheim将浮动栅极的电子隧穿到控制栅极进行电池堆积。

公开(公告)号：US06258668B1

公开(公告)日：2001-07-10

申请号：US09487501

申请日：2000-01-19

申请人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

发明人： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/115

摘要： In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

摘要翻译： 在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。 单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。 位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。 由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。 使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。 通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。

公开(公告)号：US07696018B2

公开(公告)日：2010-04-13

申请号：US12116911

申请日：2008-05-07

申请人： Antonietta Oliva ,  Louis Charles Kordus, II ,  Narbeh Derharcobian ,  Vei-Han Chan ,  Thomas E. Stewart, Jr.

发明人： Antonietta Oliva ,  Louis Charles Kordus, II ,  Narbeh Derharcobian ,  Vei-Han Chan ,  Thomas E. Stewart, Jr.

IPC分类号： H01L21/06 ,  H01L45/00

CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/126

摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，该相变材料的导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

公开(公告)号：US06674669B2

公开(公告)日：2004-01-06

申请号：US10268863

申请日：2002-10-09

申请人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

发明人： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

IPC分类号： G11C1134

CPC分类号： G11C16/08 ,  G11C8/08

摘要： In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

摘要翻译： 在非易失性存储器阵列的每行中，所有存储器单元的选择栅极连接在一起，并用于选择用于存储器存取的行。 每行的控制栅极也连接在一起，并且每行的源极区域连接在一起。 此外，多行的控制栅极连接在一起，并且多行的源极区域连接在一起，但是如果两行的源极区域连接在一起，则它们的控制栅极不连接在一起。 如果两行中的一个被访问，但是两行中的另一行未被访问，则它们的控制栅极被驱动到不同的电压，从而降低在未访问行中穿透的可能性。

公开(公告)号：US6103602A

公开(公告)日：2000-08-15

申请号：US992618

申请日：1997-12-17

申请人： Timothy J. Thurgate ,  Vei-Han Chan

发明人： Timothy J. Thurgate ,  Vei-Han Chan

IPC分类号： H01L21/8238

CPC分类号： H01L29/7881 ,  H01L29/0847 ,  H01L29/66825 ,  H01L21/823412

摘要： A system and method for providing a memory cell on a semiconductor is disclosed. The memory cell has a source and a drain. The method and system include providing a source implant in the semiconductor, providing a pocket implant in the semiconductor, and providing a drain implant in the semiconductor after the pocket implant is provided. Thus, short channel effects are reduced.

摘要翻译： 公开了一种在半导体上提供存储单元的系统和方法。 存储单元具有源极和漏极。 该方法和系统包括在半导体中提供源植入物，在半导体中提供凹穴注入，以及在提供口袋植入物之后在半导体中提供漏极注入。 因此，短通道效应降低。

公开(公告)号：US5856946A

公开(公告)日：1999-01-05

申请号：US831571

申请日：1997-04-09

申请人： Vei-Han Chan ,  Sameer Haddad ,  Chi Chang

发明人： Vei-Han Chan ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/12 ,  G11C16/04

CPC分类号： G11C16/12

摘要： A memory with controlled gate current injection during memory cell programming wherein programming circuitry applies a time-varying voltage to a control gate of the memory cell during a programming cycle. The time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate during the programming cycle.

摘要翻译： 在存储器单元编程期间具有受控栅极电流注入的存储器，其中编程电路在编程周期期间将时变电压施加到存储器单元的控制栅极。 在编程周期期间，随时间变化的电压产生从通道区域到浮动栅极的电子流量的基本恒定的速率。