公开(公告)号：US20240021713A1

公开(公告)日：2024-01-18

申请号：US18373598

申请日：2023-09-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Alexander Derrickson ,  Jagar Singh ,  Vibhor Jain ,  Andreas Knorr ,  Alexander Martin ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/735 ,  H01L29/6625 ,  H01L29/737 ,  H01L29/0808 ,  H01L29/41708 ,  H01L29/0821

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

公开(公告)号：US20240021243A1

公开(公告)日：2024-01-18

申请号：US17812485

申请日：2022-07-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chandrahasa Reddy Dinnipati ,  Bipul C. Paul ,  Ramesh Raghavan

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2213/79 ,  G11C2013/0054

Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

公开(公告)号：US11869958B2

公开(公告)日：2024-01-09

申请号：US17745280

申请日：2022-05-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Shesh Mani Pandey ,  Vibhor Jain

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7371 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector in a semiconductor substrate; a subcollector in the semiconductor substrate; an intrinsic base over the subcollector; an extrinsic base adjacent to the intrinsic base; an emitter over the intrinsic base; and an isolation structure between the extrinsic base and the emitter and which overlaps the subcollector.

公开(公告)号：US11862511B2

公开(公告)日：2024-01-02

申请号：US17527716

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli ,  Alvin Joseph

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76297 ,  H01L21/02595

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.

公开(公告)号：US20230422519A1

公开(公告)日：2023-12-28

申请号：US17847776

申请日：2022-06-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Joseph Versaggi ,  Gregory A. Northrop ,  Bipul C. Paul

IPC: H01L27/24 ,  G11C5/10 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C5/10 ,  H01L45/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a capacitor integrated with a memory element of a memory cell and methods of manufacture. The structure includes: at least one memory cell comprising a memory element with a top conductor material; and a capacitor connected to the memory element by the top conductor material.

公开(公告)号：US20230420551A1

公开(公告)日：2023-12-28

申请号：US17849867

申请日：2022-06-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Souvick Mitra ,  Anindya Nath

IPC: H01L29/745 ,  H01L29/66

CPC classification number: H01L29/7455 ,  H01L29/66363

Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.

公开(公告)号：US20230417990A1

公开(公告)日：2023-12-28

申请号：US17847399

申请日：2022-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Kevin Dezfulian ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/42

CPC classification number: G02B6/1228 ,  G02B6/4296 ,  G02B2006/12097

Abstract: Structures including a waveguide core and methods of fabricating a structure including a waveguide core. The structure comprises a photonics chip including a first chip region, a second chip region, a first waveguide core in the first chip region, and a second waveguide core in the second chip region. The first chip region adjoins the second chip region along a boundary. The first waveguide core includes a first tapered section, and the second waveguide core includes a second tapered section positioned across the boundary from the first tapered section. The first tapered section has a first width dimension that increases with increasing distance from the boundary, and the second tapered section has a second width dimension that increases with increasing distance from the boundary.

公开(公告)号：US20230405582A1

公开(公告)日：2023-12-21

申请号：US17807896

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej J. Pawlak ,  Ramsey M. Hazbun ,  Siva P. Adusumilli ,  Mark D. Levy

IPC: B01L3/00 ,  G01N27/414

CPC classification number: B01L3/502715 ,  B01L2200/12 ,  G01N27/414 ,  B01L3/502707

Abstract: Disclosed is a semiconductor structure including a monocrystalline silicon layer having a first surface and a second surface opposite the first surface. A cavity extends into the first semiconductor layer at the second surface. The structure also includes a polycrystalline silicon layer adjacent to the second surface and extending over the cavity. At least one opening extends through the second semiconductor layer to the cavity.

公开(公告)号：US11848192B2

公开(公告)日：2023-12-19

申请号：US17124012

申请日：2020-12-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/06

CPC classification number: H01L29/7373 ,  H01L29/0649 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US11846804B2

公开(公告)日：2023-12-19

申请号：US17679470

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Hemant Dixit ,  Theodore Letavic

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B2006/12061 ,  G02B2006/12135

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes an optical component having a waveguide core, and multiple features positioned adjacent to the waveguide core. The waveguide core contains a first material having a first thermal conductivity, and the features contain a second material having a second thermal conductivity that is greater than the first thermal conductivity.