公开(公告)号：US20230422519A1

公开(公告)日：2023-12-28

申请号：US17847776

申请日：2022-06-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Joseph Versaggi ,  Gregory A. Northrop ,  Bipul C. Paul

IPC: H01L27/24 ,  G11C5/10 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C5/10 ,  H01L45/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a capacitor integrated with a memory element of a memory cell and methods of manufacture. The structure includes: at least one memory cell comprising a memory element with a top conductor material; and a capacitor connected to the memory element by the top conductor material.

公开(公告)号：US20230420551A1

公开(公告)日：2023-12-28

申请号：US17849867

申请日：2022-06-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Souvick Mitra ,  Anindya Nath

IPC: H01L29/745 ,  H01L29/66

CPC classification number: H01L29/7455 ,  H01L29/66363

Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.

公开(公告)号：US20230417990A1

公开(公告)日：2023-12-28

申请号：US17847399

申请日：2022-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Kevin Dezfulian ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/42

CPC classification number: G02B6/1228 ,  G02B6/4296 ,  G02B2006/12097

Abstract: Structures including a waveguide core and methods of fabricating a structure including a waveguide core. The structure comprises a photonics chip including a first chip region, a second chip region, a first waveguide core in the first chip region, and a second waveguide core in the second chip region. The first chip region adjoins the second chip region along a boundary. The first waveguide core includes a first tapered section, and the second waveguide core includes a second tapered section positioned across the boundary from the first tapered section. The first tapered section has a first width dimension that increases with increasing distance from the boundary, and the second tapered section has a second width dimension that increases with increasing distance from the boundary.

公开(公告)号：US20230405582A1

公开(公告)日：2023-12-21

申请号：US17807896

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej J. Pawlak ,  Ramsey M. Hazbun ,  Siva P. Adusumilli ,  Mark D. Levy

IPC: B01L3/00 ,  G01N27/414

CPC classification number: B01L3/502715 ,  B01L2200/12 ,  G01N27/414 ,  B01L3/502707

Abstract: Disclosed is a semiconductor structure including a monocrystalline silicon layer having a first surface and a second surface opposite the first surface. A cavity extends into the first semiconductor layer at the second surface. The structure also includes a polycrystalline silicon layer adjacent to the second surface and extending over the cavity. At least one opening extends through the second semiconductor layer to the cavity.

公开(公告)号：US11848192B2

公开(公告)日：2023-12-19

申请号：US17124012

申请日：2020-12-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/06

CPC classification number: H01L29/7373 ,  H01L29/0649 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US11846804B2

公开(公告)日：2023-12-19

申请号：US17679470

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Hemant Dixit ,  Theodore Letavic

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B2006/12061 ,  G02B2006/12135

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes an optical component having a waveguide core, and multiple features positioned adjacent to the waveguide core. The waveguide core contains a first material having a first thermal conductivity, and the features contain a second material having a second thermal conductivity that is greater than the first thermal conductivity.

公开(公告)号：US20230402453A1

公开(公告)日：2023-12-14

申请号：US18231510

申请日：2023-08-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  John J. ELLIS-MONAGHAN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK

IPC: H01L27/082 ,  H01L27/06 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L27/082 ,  H01L27/0647 ,  H01L29/737 ,  H01L29/0646

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US11841103B2

公开(公告)日：2023-12-12

申请号：US17226087

申请日：2021-04-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas Shellenberger ,  Michael Scalise

IPC: F16L41/08 ,  F16L41/02

CPC classification number: F16L41/08 ,  F16L41/02

Abstract: A pipe assembly is provided, the pipe assembly comprising a first pipe having a side opening on a side surface of the first pipe. A plate in the first pipe is arranged adjacent to the side opening and at an angle relative to a radial axis of the first pipe such that a first side of the plate may be lower than a second side. A vent hole may be proximal the side opening on the side surface of the first pipe.

公开(公告)号：US11837605B2

公开(公告)日：2023-12-05

申请号：US17644858

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tom Herrmann ,  Zhixing Zhao ,  Alban Zaka ,  Yiching Chen

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/7838

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.

公开(公告)号：US11837547B2

公开(公告)日：2023-12-05

申请号：US17450324

申请日：2021-10-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Roderick Alan Augur ,  Yusheng Bian ,  Robert John Fox, III

IPC: H01L23/532 ,  H01L23/552 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L23/5226 ,  H01L23/552

Abstract: A photonic integrated circuit (PIC) die includes a silicon nitride optical component over an active region. Multiple interconnect layers are over the silicon nitride optical component, each of the multiple interconnect layers including a metal interconnect therein. At least one optical deflector is over the multiple interconnect layers and over the silicon nitride optical component. The optical deflector(s) may also include a contact passing therethrough to the interconnect layers, but do not include any other electrical interconnects. Each optical deflector may deflect light within an ambient light range of less than 570 nanometers (nm) to protect the silicon nitride optical component from light-induced degradation.