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    Semiconductor device and a method of manufacturing the same
    111.
    发明授权
    Semiconductor device and a method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07465981B2

    公开(公告)日：2008-12-16

    申请号：US11116190

    申请日：2005-04-28

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L27/108

    CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7687 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/40

    Abstract: A semiconductor device includes a semiconductor substrate; a first electrode formed over the semiconductor substrate; a first insulation film covering the first electrode and having an aperture for exposing a part of the first electrode; a first conductive film formed on a part of the first insulation film and the first electrode inside the aperture; an isolation region placed inside the aperture; and a second conductive film formed on the first conductive film and the isolation region.

    Abstract translation: 半导体器件包括半导体衬底; 形成在半导体衬底上的第一电极; 覆盖所述第一电极并具有用于暴露所述第一电极的一部分的孔的第一绝缘膜; 形成在第一绝缘膜的一部分上的第一导电膜和孔内的第一电极; 放置在孔内的隔离区; 以及形成在第一导电膜和隔离区上的第二导电膜。

    Thin film piezoelectric actuator
    112.
    发明授权
    Thin film piezoelectric actuator 失效
    薄膜压电致动器

    公开(公告)号：US07459833B2

    公开(公告)日：2008-12-02

    申请号：US11054404

    申请日：2005-02-10

    Applicant: Takashi Kawakubo ,  Ryoichi Ohara ,  Tomio Ono ,  Toshihiko Nagano ,  Michihiko Nishigaki ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Kenya Sano

    Inventor： Takashi Kawakubo ,  Ryoichi Ohara ,  Tomio Ono ,  Toshihiko Nagano ,  Michihiko Nishigaki ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Kenya Sano

    IPC: H01L41/08

    CPC classification number: H01G7/06 ,  H01H2057/006 ,  H01L41/0933 ,  H01L41/094

    Abstract: A thin film piezoelectric actuator comprises a driving part at least one end of which is supported by an anchor portion. The driving part includes: a piezoelectric film, a first lower electrode provided under a first region of the piezoelectric film, a second lower electrode provided under a second region different from the first region of the piezoelectric film, a first upper electrode provided opposite to the first lower electrode on the piezoelectric film, a second upper electrode provided opposite to the second lower electrode on the piezoelectric film, a first connection part that electrically connects the first lower electrode and the second upper electrode via a first via hole formed in the piezoelectric film, and a second connection part that electrically connects the second lower electrode and the first upper electrode via a second via hole formed in the piezoelectric film.

    Abstract translation: 薄膜压电致动器包括驱动部件，其至少一端由锚固部分支撑。 驱动部包括：压电膜，设置在压电膜的第一区域下方的第一下电极，设置在与压电膜的第一区不同的第二区域下方的第二下电极，与第一下电极相对设置的第一上电极 压电膜上的第一下电极，与压电膜上的第二下电极相对设置的第二上电极，经由形成在压电膜中的第一通孔电连接第一下电极和第二上电极的第一连接部 以及第二连接部，其经由形成在所述压电膜中的第二通路孔电连接所述第二下部电极和所述第一上部电极。

    Semiconductor device and method for fabricating the same
    114.
    发明申请
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US20080061399A1

    公开(公告)日：2008-03-13

    申请号：US11826331

    申请日：2007-07-13

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L29/00

    CPC classification number: H01L27/11502 ,  H01L27/11507

    Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; a capacitor having a lower electrode formed on said semiconductor substrate, a capacity insulating film formed on said lower electrode, and an upper electrode formed on said capacity insulating film; contact holes formed on said upper electrode and said lower electrode; a barrier layer containing oxygen, formed inside said contact holes; and a conductive layer which fills said contact holes in which said barrier layer is formed on the inside.

    Abstract translation: 根据本发明的半导体器件包括半导体衬底; 形成在所述半导体衬底上的下电极的电容器，形成在所述下电极上的电容绝缘膜和形成在所述电容绝缘膜上的上电极; 形成在所述上电极和所述下电极上的接触孔; 在所述接触孔内形成含有氧的阻挡层; 以及填充在内部形成有阻挡层的所述接触孔的导电层。

    THIN FILM PIEZOELECTRIC ACTUATOR
    115.
    发明申请
    THIN FILM PIEZOELECTRIC ACTUATOR 失效
    薄膜压电致动器

    公开(公告)号：US20070278900A1

    公开(公告)日：2007-12-06

    申请号：US11781667

    申请日：2007-07-23

    Applicant: Takashi KAWAKUBO ,  Ryoichi Ohara ,  Tomio Ono ,  Toshihiko Nagano ,  Michihiko Nishigaki ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Kenya Sano

    Inventor： Takashi KAWAKUBO ,  Ryoichi Ohara ,  Tomio Ono ,  Toshihiko Nagano ,  Michihiko Nishigaki ,  Takaaki Yasumoto ,  Kazuhide Abe ,  Kenya Sano

    IPC: H01L41/08

    CPC classification number: H01G7/06 ,  H01H2057/006 ,  H01L41/0933 ,  H01L41/094

    Abstract: A thin film piezoelectric actuator comprises a driving part at least one end of which is supported by an anchor portion. The driving part includes: a piezoelectric film, a first lower electrode provided under a first region of the piezoelectric film, a second lower electrode provided under a second region different from the first region of the piezoelectric film, a first upper electrode provided opposite to the first lower electrode on the piezoelectric film, a second upper electrode provided opposite to the second lower electrode on the piezoelectric film, a first connection part that electrically connects the first lower electrode and the second upper electrode via a first via hole formed in the piezoelectric film, and a second connection part that electrically connects the second lower electrode and the first upper electrode via a second via hole formed in the piezoelectric film.

    Abstract translation: 薄膜压电致动器包括驱动部件，其至少一端由锚固部分支撑。 驱动部包括：压电膜，设置在压电膜的第一区域下方的第一下电极，设置在与压电膜的第一区不同的第二区域下方的第二下电极，与第一下电极相对设置的第一上电极 压电膜上的第一下电极，与压电膜上的第二下电极相对设置的第二上电极，经由形成在压电膜中的第一通孔电连接第一下电极和第二上电极的第一连接部 以及第二连接部，其经由形成在所述压电膜中的第二通路孔电连接所述第二下部电极和所述第一上部电极。

    Voltage controlled oscillator
    117.
    发明申请
    Voltage controlled oscillator 失效
    压控振荡器

    公开(公告)号：US20050099236A1

    公开(公告)日：2005-05-12

    申请号：US10935264

    申请日：2004-09-08

    Applicant: Takashi Kawakubo ,  Kazuhide Abe ,  Mayumi Morizuka

    Inventor： Takashi Kawakubo ,  Kazuhide Abe ,  Mayumi Morizuka

    IPC: H03B5/30 ,  H03B5/32 ,  H03B5/36 ,  H03H9/02 ,  H03H9/05 ,  H03H9/17 ,  H03H9/00

    CPC classification number: H03H9/173 ,  H03B5/326 ,  H03B5/366 ,  H03H9/0542 ,  H03H2009/02204 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/49005 ,  Y10T29/49155

    Abstract: The present invention provides a voltage controlled oscillator comprising an thin film BAW resonator and a variable capacitor element. The thin film BAW resonator includes an anchor section formed on a Si substrate, a lower electrode supported on the anchor section and positioned to face the Si substrate, a first piezoelectric film formed on the lower electrode, and an upper electrode formed on the first piezoelectric film. On the other hand, the variable capacitor element includes a stationary electrode formed on a Si substrate, an anchor section formed on the Si substrate, a first electrode supported on the anchor section and positioned to face the Si substrate, a second piezoelectric film formed on the first electrode, and a second electrode formed on the second piezoelectric film.

    Abstract translation: 本发明提供一种包括薄膜BAW谐振器和可变电容器元件的压控振荡器。 薄膜BAW谐振器包括形成在Si衬底上的锚定部分，支撑在锚固部分上并定位成面对Si衬底的下电极，形成在下电极上的第一压电膜，以及形成在第一压电 电影。 另一方面，可变电容器元件包括形成在Si衬底上的固定电极，形成在Si衬底上的锚定部分，支撑在锚定部分上并且定位成面对Si衬底的第一电极，形成在第二压电膜上的第二压电膜 第一电极和形成在第二压电膜上的第二电极。

    Method of forming metal wiring
    118.
    发明授权
    Method of forming metal wiring 失效
    形成金属布线的方法

    公开(公告)号：US06770560B2

    公开(公告)日：2004-08-03

    申请号：US10444986

    申请日：2003-05-27

    Applicant: Kazuhide Abe

    Inventor： Kazuhide Abe

    IPC: H01L2144

    CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate including an insulating layer is provided. A groove is formed on the insulating layer. An additive-containing barrier layer is formed on the insulating layer. A metal seed layer and a metal layer are formed on the barrier layer. Then, the metal layer is subjected to a first heat treatment at a first temperature that is capable of promoting grain growth of the metal seed layer and the metal layer. The barrier layer, the metal seed layer and the metal layer are partially removed so that a conductive layer including the metal seed layer and the metal layer is formed in the groove. Finally, the conductive layer is subjected to a second heat treatment at a second temperature that is higher than the first temperature and allows an additive element in the barrier layer to diffuse into the metal layer.

    Abstract translation: 在制造半导体器件的方法中，提供了包括绝缘层的半导体衬底。 在绝缘层上形成凹槽。 在绝缘层上形成含添加剂的阻挡层。 在阻挡层上形成金属种子层和金属层。 然后，在能够促进金属种子层和金属层的晶粒生长的第一温度下对金属层进行第一次热处理。 部分去除阻挡层，金属种子层和金属层，使得在沟槽中形成包括金属籽晶层和金属层的导电层。 最后，在高于第一温度的第二温度下对导电层进行第二次热处理，并允许阻挡层中的添加元素扩散到金属层中。

    Non-volatile semiconductor integrated memory device
    120.
    发明授权
    Non-volatile semiconductor integrated memory device 失效
    非易失性半导体集成存储器件

    公开(公告)号：US06198652B1

    公开(公告)日：2001-03-06

    申请号：US09289940

    申请日：1999-04-13

    Applicant: Takashi Kawakubo ,  Kazuhide Abe ,  Daisaburo Takashima

    Inventor： Takashi Kawakubo ,  Kazuhide Abe ,  Daisaburo Takashima

    IPC: G11C1122

    CPC classification number: H01L27/11502 ,  G11C11/22 ,  G11C11/223

    Abstract: A semiconductor integrated memory device comprises a plurality of memory cell blocks, which are formed in the form of a matrix and each of which comprises: a memory cell chain including a plurality of units, each comprising a ferroelectric memory capacitor and a control transistor connected in parallel thereto; a reference capacitor of a unit comprising a reference capacitor and a control transistor connected in parallel thereto; a read transistor having a gate electrode connected to a connection point between the memory cell chain and the reference cell; and a control transistor for adjusting potentials of storage node which is a connection point of the first electrode of the memory capacitor, the third electrode of the reference capacitor and the read transistor. With this construction, the semiconductor integrated memory device is able to be easily produced, to stably retain a ferroelectric polarization and to scale down.

    Abstract translation: 半导体集成存储器件包括以矩阵形式形成的多个存储器单元块，每个存储单元块包括：包括多个单元的存储单元链，每个单元包括铁电存储电容器和连接在其上的控制晶体管 平行于 包括参考电容器和与其并联连接的控制晶体管的单元的参考电容器; 读取晶体管，其具有连接到存储器单元链和参考单元之间的连接点的栅电极; 以及用于调整作为存储电容器的第一电极，参考电容器的第三电极和读取晶体管的连接点的存储节点的电位的控制晶体管。 利用这种结构，能够容易地制造半导体集成存储器件，以稳定地保持铁电极化并缩小。

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