公开(公告)号：US06198652B1

公开(公告)日：2001-03-06

申请号：US09289940

申请日：1999-04-13

申请人： Takashi Kawakubo ,  Kazuhide Abe ,  Daisaburo Takashima

发明人： Takashi Kawakubo ,  Kazuhide Abe ,  Daisaburo Takashima

IPC分类号： G11C1122

CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C11/223

摘要： A semiconductor integrated memory device comprises a plurality of memory cell blocks, which are formed in the form of a matrix and each of which comprises: a memory cell chain including a plurality of units, each comprising a ferroelectric memory capacitor and a control transistor connected in parallel thereto; a reference capacitor of a unit comprising a reference capacitor and a control transistor connected in parallel thereto; a read transistor having a gate electrode connected to a connection point between the memory cell chain and the reference cell; and a control transistor for adjusting potentials of storage node which is a connection point of the first electrode of the memory capacitor, the third electrode of the reference capacitor and the read transistor. With this construction, the semiconductor integrated memory device is able to be easily produced, to stably retain a ferroelectric polarization and to scale down.

摘要翻译： 半导体集成存储器件包括以矩阵形式形成的多个存储器单元块，每个存储单元块包括：包括多个单元的存储单元链，每个单元包括铁电存储电容器和连接在其上的控制晶体管 平行于 包括参考电容器和与其并联连接的控制晶体管的单元的参考电容器; 读取晶体管，其具有连接到存储器单元链和参考单元之间的连接点的栅电极; 以及用于调整作为存储电容器的第一电极，参考电容器的第三电极和读取晶体管的连接点的存储节点的电位的控制晶体管。 利用这种结构，能够容易地制造半导体集成存储器件，以稳定地保持铁电极化并缩小。

公开(公告)号：US08792266B2

公开(公告)日：2014-07-29

申请号：US13605674

申请日：2012-09-06

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： A memory cell is formed with a resistance variable element, which is interposed between first and second electrodes and can store resistance changes representing 2 or more different values, and first and second cell transistors having source terminals thereof connected to the first electrode, and gates thereof to a word line. A drain of the first cell transistor is connected to a bit line, and a drain of the second cell transistor is connected to a data line. The second electrode is connected to a source line. During a read operation, the first and second cell transistors are kept in an ON state, and a current is supplied from the bit line to the source line through the memory cell. Data is read according to the electrical potential difference between the data line and the source line.

摘要翻译： 存储单元形成有电阻可变元件，其被插入在第一和第二电极之间，并且可以存储表示2个或更多个不同值的电阻变化，以及其源极端子连接到第一电极的第一和第二单元晶体管及其栅极 到一个字线。 第一单元晶体管的漏极连接到位线，并且第二单元晶体管的漏极连接到数据线。 第二电极连接到源极线。 在读取操作期间，第一和第二单元晶体管保持在导通状态，并且通过存储单元从位线向源极线提供电流。 根据数据线和源极线之间的电位差读取数据。

公开(公告)号：US08650373B2

公开(公告)日：2014-02-11

申请号：US12860160

申请日：2010-08-20

申请人： Kosuke Hatsuda ,  Daisaburo Takashima

发明人： Kosuke Hatsuda ,  Daisaburo Takashima

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F11/1441

摘要： According to one embodiment, a memory system includes a nonvolatile first memory, a nonvolatile second memory, a data-copy processing unit and a data invalidation processing unit. The first memory has a storage capacity for n (n≧2) pages per word line. The nonvolatile second memory temporarily stores user data write-requested from a host apparatus. The data-copy processing unit executes data copy processing including reading out, in page units, the user data stored in the second memory and sequentially writing the read-out user data in page units in the first memory. The data invalidation processing unit selects, after the execution of the data copy processing, based on whether the memory cell group per word line stores user data for n pages, user data requiring backup out of the user data subjected to the data copy processing and leaves the selected user data in the second memory as backup data.

摘要翻译： 根据一个实施例，存储器系统包括非易失性第一存储器，非易失性第二存储器，数据复制处理单元和数据无效化处理单元。 第一个存储器具有每个字线n（n> = 2）页的存储容量。 非易失性第二存储器临时存储从主机装置写入请求的用户数据。 数据复制处理单元执行数据复制处理，包括以页为单位读出存储在第二存储器中的用户数据，并以页单元顺序地将读出的用户数据写入第一存储器。 数据无效处理单元在执行数据复制处理之后，根据每个字线的存储单元组是否存储n页的用户数据，选择需要备份的用户数据进行数据复制处理的用户数据，并且离开 所选择的用户数据在第二存储器中作为备份数据。

公开(公告)号：US08559223B2

公开(公告)日：2013-10-15

申请号：US13049504

申请日：2011-03-16

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/40

CPC分类号： G11C14/0018 ,  G11C14/00 ,  G11C16/04 ,  G11C16/0408 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11529

摘要： According to one embodiment, there is provided a fusion memory including a first memory cell array formed of a NAND cell unit and a second memory cell array formed of a DRAM cell on a semiconductor substrate. The NAND cell unit is formed of a non-volatile memory cell having a two-layer gate structure in which a first gate and a second gate are stacked, and a selective transistor connecting the first and second gates of the non-volatile memory cell. The DRAM cell is formed of a cell transistor having a structure same as the structure of the selective transistor, and a MOS capacitor having a structure same as the structure of the non-volatile memory cell or the selective transistor.

摘要翻译： 根据一个实施例，提供了一种融合存储器，包括由NAND单元单元形成的第一存储单元阵列和由半导体衬底上的DRAM单元形成的第二存储单元阵列。 NAND单元单元由具有堆叠第一栅极和第二栅极的双层栅极结构的非易失性存储单元和连接非易失性存储单元的第一和第二栅极的选择晶体管构成。 DRAM单元由具有与选择晶体管的结构相同的单元晶体管和具有与非易失性存储单元或选择晶体管的结构相同的结构的MOS电容器形成。

公开(公告)号：US08255762B2

公开(公告)日：2012-08-28

申请号：US13297327

申请日：2011-11-16

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

IPC分类号： H03M13/00

CPC分类号： G11C16/349 ,  G06F11/1068 ,  G11C11/005 ,  G11C16/3431

摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

摘要翻译： 本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取的数据被写回同一个存储器组时，当错误位计数超过第一阈值时 或者当数据读取计数超过第二阈值时。

公开(公告)号：US08156393B2

公开(公告)日：2012-04-10

申请号：US12513860

申请日：2007-11-28

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

IPC分类号： G11C29/00

CPC分类号： G11C16/349 ,  G06F11/008 ,  G06F11/1068

摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

摘要翻译： 提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。 存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量 擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数， 诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。

公开(公告)号：US08134349B2

公开(公告)日：2012-03-13

申请号：US12404438

申请日：2009-03-16

申请人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G05F1/613

CPC分类号： G05F1/56

摘要： A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.

摘要翻译： 电源电路具有恒压电路，第一MOS晶体管，第二MOS晶体管，第三MOS晶体管，第一分压电路，输出通过将输出端子的电压除以第一分压而得到的第一分压 以及馈送有参考电压的第一差分放大器电路和第一分压，并且具有连接到第二MOS晶体管的栅极的输出。 当第一分压高于参考电压时，第一差分放大器电路输出信号以接通第二MOS晶体管，并且当第一分压电压较低时，第一差分放大器电路输出关闭第二MOS晶体管的信号 比参考电压。

公开(公告)号：US08116112B2

公开(公告)日：2012-02-14

申请号：US12553048

申请日：2009-09-02

申请人： Tadashi Miyakawa ,  Daisaburo Takashima

发明人： Tadashi Miyakawa ,  Daisaburo Takashima

IPC分类号： G11C5/06

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2207/002 ,  G11C2207/005

摘要： A semiconductor memory apparatus includes: a bit line; a word line; a local bit line; a first switch unit provided between the local bit line and the bit; a memory cell connected to the bit line and the word line; a memory cell array including the memory cell; a first sense circuit connected to the bit line and configured to amplify a signal read out from the memory cell; and a second sense circuit connected to the local bit lines and configured to amplify a signal amplified by the first sense circuit, wherein the first switch unit disconnects the local bit line from the bit line when the first sense circuit amplifies the signal, and connects the local bit line to the bit line when the second sense circuit amplifies the signal amplified by the first sense circuit.

摘要翻译： 一种半导体存储装置，包括：位线; 字线 一个局部位线; 设置在本地位线和位之间的第一开关单元; 连接到位线和字线的存储单元; 包括存储单元的存储单元阵列; 连接到所述位线并被配置为放大从所述存储单元读出的信号的第一感测电路; 以及连接到本地位线并被配置为放大由第一感测电路放大的信号的第二感测电路，其中当第一感测电路放大信号时，第一开关单元将位置线与位线断开连接， 当第二感测电路放大由第一感测电路放大的信号时，到位线的局部位线。

公开(公告)号：US08078923B2

公开(公告)日：2011-12-13

申请号：US12523607

申请日：2008-09-30

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

IPC分类号： G06F11/00

CPC分类号： G11C16/349 ,  G06F11/1068 ,  G11C11/005 ,  G11C16/3431

摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

摘要翻译： 本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取数据写入同一存储器组时，当错误位计数超过第一阈值时 或者当数据读取计数超过第二阈值时。

公开(公告)号：US08064240B2

公开(公告)日：2011-11-22

申请号：US12502929

申请日：2009-07-14

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： G11C11/22

摘要： A memory includes word lines; plate lines; first to eighth bit lines; cell transistors; ferroelectric capacitor connected in parallel with cell transistors; sense amplifiers, wherein cell transistors and ferroelectric capacitors configure cells, the cells are connected in series to configure first to eighth cell blocks, the cell blocks are connected to the same word lines, first ends of the cell blocks are respectively connected to the bit lines, second ends of the cell blocks are respectively connected to the different plate lines, one of the first to the fourth bit lines and one of the fifth to the eighth bit lines are configured to be selectively connected to the sense amplifier during an operation, numbers of the cells connected in series between the bit lines and the plate lines are different in the first to the fourth cell blocks, and are different in the fifth to the eighth cell blocks.

摘要翻译： 存储器包括字线; 板条线 第一到第八位; 单元晶体管; 铁电电容器与电池晶体管并联; 读出放大器，其中单元晶体管和铁电电容器配置单元，单元串联连接以配置第一至第八单元块，单元块连接到相同的字线，单元块的第一端分别连接到位线 ，单元块的第二端分别连接到不同的板线，第一至第四位线之一和第五至第八位线之一被配置为在操作期间选择性地连接到读出放大器，数字 串联连接在位线和板线之间的单元在第一至第四单元块中不同，并且在第五至第八单元块中不同。