公开(公告)号：US08742848B1

公开(公告)日：2014-06-03

申请号：US13829567

申请日：2013-03-14

Applicant: Linear Technology Corporation

Inventor： Thomas Lloyd Botker

IPC: H03F3/45

CPC classification number: H03F3/4508 ,  H03F3/45618 ,  H03F2200/261 ,  H03F2203/45356

Abstract: A method of fabricating an instrumentation amplifier to have an improved common mode rejection ratio (CMRR) vs. frequency initially trims resistors in the input amplifiers of the instrumentation amplifier during a DC test, where the inputs are shorted and a DC voltage is applied, so that the output of the amplifier is approximately zero. This will normally cause the transconductances of the two input amplifiers to be different. Thus, the AC CMRR will degrade with frequency. Trimmable capacitors are provided in the input section and are trimmed during a common mode AC test to cause the output voltage to be minimized during the AC test. This causes the two input amplifiers to have the same bandwidth and gm/C ratio.

Abstract translation: 在直流测试期间，在输入短路和施加直流电压的情况下，制造具有改进的共模抑制比（CMRR）与频率的仪器放大器的方法最初对仪表放大器的输入放大器中的电阻器进行微调，因此 放大器的输出大约为零。 这通常会导致两个输入放大器的跨导不同。 因此，AC CMRR将随着频率而降级。 在输入部分提供了可调电容器，并在共模交流测试期间进行了修整，以在AC测试期间使输出电压最小化。 这使得两个输入放大器具有相同的带宽和gm / C比。

公开(公告)号：US20140139198A1

公开(公告)日：2014-05-22

申请号：US13764045

申请日：2013-02-11

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Gregory Manlove ,  Yi Ding Gu ,  Jian Li

IPC: G05F1/10

CPC classification number: G05F1/10 ,  G05F1/562 ,  H02M1/32 ,  H02M3/142 ,  H02M3/156 ,  H02M3/158 ,  H02M2001/0019 ,  H02M2001/0025

Abstract: A switching regulator circuit incorporates an offset circuit, connected in a control loop of the regulator circuit, that, in response to a signal indicating an imminent load current step, adjusts a duty cycle of a power switch for the current step prior to the regulator circuit responding to a change in output voltage due to the current step. In one embodiment, a load controller issues a digital signal shortly before a load current step. The digital signal is decoded and converted to an analog offset signal in a feedback control loop of the regulator to immediately adjust a duty cycle of the switch irrespective of the output voltage level. By proper timing of the offset, output voltage ripple is greatly reduced. The current offset may also be used to rapidly change the output voltage in response to an external signal requesting a voltage step.

Abstract translation: 开关稳压器电路包括连接在调节器电路的控制回路中的偏移电路，响应于指示迫在眉睫的负载电流步长的信号，调节调节器电路之前的当前步骤的功率开关的占空比 响应于由于当前步骤而导致的输出电压的变化。 在一个实施例中，负载控制器在负载电流步长之前不久就发出数字信号。 数字信号被解码并转换成调节器的反馈控制环路中的模拟偏移信号，以立即调节开关的占空比，而与输出电压电平无关。 通过适当的偏移定时，输出电压纹波大大降低。 电流偏移也可以用于响应于请求电压阶跃的外部信号快速地改变输出电压。

公开(公告)号：US20140132431A1

公开(公告)日：2014-05-15

申请号：US14162567

申请日：2014-01-23

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Jesper STEENSGAARD-MADSEN

IPC: H03M1/20

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/0668 ,  H03M1/462 ,  H03M1/468

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract translation: 一种模数转换器（ADC）系统和方法。 根据一个实施例的ADC系统包括被配置为对模拟信号值和模拟抖动值的组合进行采样的采样数模转换器，以及包括失配整形编码器的控制电路。 控制电路被配置为在模数转换操作期间将多个数字代码顺序地应用于采样数模转换器，以导出表示模拟信号值和模拟抖动值的组合的数字代码。 呈现了几个实施例。

公开(公告)号：US20130257538A1

公开(公告)日：2013-10-03

申请号：US13857935

申请日：2013-04-05

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Dave Thomas

IPC: H03F3/45

CPC classification number: H03F3/45071 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2200/405 ,  H03F2203/45101 ,  H03F2203/45634 ,  H03F2203/45726 ,  H03M1/1023 ,  H03M1/164

Abstract: A common mode bias circuit may include a weak common mode bias generator and a common mode bias capacitance. During a first state of the common mode bias circuit, the weak common mode bias generator may be coupled to the common mode bias capacitance and may impart to them a predefined common mode signal level. During a second state of the common mode bias circuit, the common mode bias capacitance may be coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier.

Abstract translation: 共模偏置电路可以包括弱共模偏置发生器和共模偏置电容。 在共模偏置电路的第一状态期间，弱共模偏置发生器可以耦合到共模偏置电容，并且可以向它们赋予预定的共模信号电平。 在共模偏置电路的第二状态期间，可以以确定放大器的输入共模电平的方式将共模偏置电容耦合到放大器的差分输入。

公开(公告)号：US20040090355A1

公开(公告)日：2004-05-13

申请号：US10695679

申请日：2003-10-28

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Michael Keith Mayes

IPC: H03M003/00

CPC classification number: H03M3/498 ,  H03M3/462

Abstract: Circuits and methods for a delta-sigma analog-to-digital converter having a variable oversample ratio to produce a constant fullscale output at reduced circuit complexity, die area, and power dissipation are provided. The circuits and methods consist of scaling the digital input to the digital filter with a decoder whose size depends on the number of oversample ratios allowed by the analog-to-digital converter. The digital filter is implemented as a comb filter having a cascade of N integrators and N differentiators, where N is the order of the digital filter. The size of the differentiators is equal to the number of bits used as output for the analog-to-digital converter, which is smaller than the size of the integrators and the number of bits produced by the digital filter.

Abstract translation: 提供了具有可变过采样比率的delta-sigma模数转换器的电路和方法，以在降低的电路复杂度，管芯面积和功率耗散下产生恒定的满量程输出。 电路和方法包括使用解码器将数字输入缩放到数字滤波器，该解码器的大小取决于模拟 - 数字转换器允许的过采样比数。 数字滤波器被实现为具有级联的N个积分器和N个微分器的梳状滤波器，其中N是数字滤波器的阶数。 微分器的尺寸等于用作模数转换器的输出的位数，该位数小于积分器的大小和数字滤波器产生的位数。

公开(公告)号：US20030090240A1

公开(公告)日：2003-05-15

申请号：US10324628

申请日：2002-12-18

Applicant: Linear Technology Corporation

Inventor： Jeffrey Schenkel ,  Albert M. Wu ,  Robert C. Dobkin ,  Steven M. Pietkiewicz

IPC: H02J001/00

CPC classification number: H05B41/30 ,  H02M3/33507

Abstract: The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

公开(公告)号：US20030025484A1

公开(公告)日：2003-02-06

申请号：US10261916

申请日：2002-09-30

Applicant: Linear Technology Corporation

Inventor： Karl Edwards

IPC: G05F001/40

CPC classification number: G05F1/573 ,  H02M3/33507

Abstract: A current-mode switching regulator that maintains a substantially constant maximum current limit over a virtually full range of duty cycles is provided. The regulator has a control circuit that includes a buffer circuit, an adjustable voltage clamp circuit, and a slope compensation circuit. The buffer circuit isolates a control signal from capacitive loading associated with control circuit. The threshold level of the adjustable voltage clamp circuit varies with respect to the amount of slope compensation provided to the voltage regulator. This allows a control voltage to increase as slope compensation increases so that a substantially constant maximum current limit is maintained.

公开(公告)号：US20020180413A1

公开(公告)日：2002-12-05

申请号：US10197357

申请日：2002-07-15

Applicant: Linear Technology Corporation

Inventor： Christopher B. Umminger ,  Randy G. Flatness

IPC: G05F001/40

CPC classification number: H02M3/1584

Abstract: Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.

Abstract translation: 公开了用于使非恒定频率开关调节器与锁相环同步的方法。 这些方法使得非恒定频率开关调节器能够与锁相环同步，以在稳态下实现恒定频率运行，同时保持非频率运算的优点，以改善瞬态响应并在更宽范围的占空比下工作。 此外，这种方法使多个非恒定频率调节器能够同步并行并行运行，从而为单个开关稳压器提供比输出更高的功率电平。

公开(公告)号：US20020163255A1

公开(公告)日：2002-11-07

申请号：US10180418

申请日：2002-06-24

Applicant: Linear Technology Corporation

Inventor： David Henry Soo ,  Robert Loren Reay

IPC: H02J001/10

CPC classification number: H02J1/102 ,  H02H9/004 ,  Y10T307/549 ,  Y10T307/555 ,  Y10T307/604

Abstract: Circuits and methods for controlling load sharing by multiple power supplies are provided. In preferred embodiments, load share controllers utilize multiple voltage control loops to monitor the output voltages that are being provided by multiple power supplies connected to a load. These voltage control loops each generate a voltage control voltage that is proportional to the difference between the actual output voltage of the corresponding power supply and the desired output voltage. The voltage control loop with the highest voltage control voltage then controls a current control voltage generated in a current control loop for each power supply via a share bus. These current control loops then regulate the current provided by the corresponding power supplies so that those currents are all proportional to the voltage on the share bus. By monitoring the current control voltage in each current control loop, the voltage at the output of each power supply, and the direction of the current flowing between each power supply and the load, the circuits and methods of preferred embodiments of the invention can detect and account for out-of-regulation conditions, over voltage conditions, short circuit conditions, and hot-swapping conditions.

公开(公告)号：US20020041217A1

公开(公告)日：2002-04-11

申请号：US09988930

申请日：2001-11-21

Applicant: Linear Technology Corporation

Inventor： Andrew H. Crofts ,  Michael A. Kultgen

IPC: H03L001/00

CPC classification number: H03K3/0231 ,  H03K4/023 ,  H03L7/00

Abstract: A precision oscillator circuit providing a periodic waveform is provided. A periodic waveform is provided by the use of an integrating op-amp circuit in conjunction with a switched capacitor frequency control loop and a user input adapted to be coupled with a frequency-setting resistor. The frequency of the periodic waveform is determined by the values of the switched capacitor and the resistor. The oscillator circuit has an arrangement which minimizes the effect of the op-amp circuit's offset voltage. The user input is kept robust against user-introduced capacitance by the use of controllable current sources and/or controllable voltage sources to bias the op-amp circuit. A linearity correction circuit is also provided to correct for non-ideal op-amp circuits.

Abstract translation: 提供提供周期波形的精密振荡器电路。 通过使用集成运算放大器电路与开关电容器频率控制回路和适于与频率设定电阻器耦合的用户输入来提供周期性波形。 周期波形的频率由开关电容器和电阻器的值决定。 振荡器电路具有最小化运算放大器电路的偏移电压的影响的布置。 通过使用可控电流源和/或可控电压源来偏置运算放大器电路，用户输入对用户引入的电容保持稳定。 还提供线性校正电路来校正非理想运算放大器电路。