公开(公告)号：US20240258378A1

公开(公告)日：2024-08-01

申请号：US18632253

申请日：2024-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hua Chang ,  Jian-Feng Li ,  Hsiang-Chieh Yen

IPC: H01L29/15 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/157 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30625 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

公开(公告)号：US12052932B2

公开(公告)日：2024-07-30

申请号：US18132989

申请日：2023-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.

公开(公告)号：US12051740B2

公开(公告)日：2024-07-30

申请号：US17367640

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0649 ,  H01L29/66462 ,  H01L29/6656

Abstract: A high electron mobility transistor includes an epitaxial stack on a substrate, a gate structure on the epitaxial stack, a passivation layer on the epitaxial stack and covering the gate structure, and an air gap between the passivation layer and the gate structure.

公开(公告)号：US12046671B2

公开(公告)日：2024-07-23

申请号：US17569527

申请日：2022-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Hua Chang ,  Shin-Hung Li ,  Tsung-Yu Yang ,  Ruei-Jhe Tsao

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/66704

Abstract: A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.

公开(公告)号：US12040392B2

公开(公告)日：2024-07-16

申请号：US18075427

申请日：2022-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Ming-Hua Chang ,  Shui-Yen Lu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

公开(公告)号：US12040370B2

公开(公告)日：2024-07-16

申请号：US17376151

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Cheng Hung ,  Yu-Jen Liu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/823437 ,  H01L29/78

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a gate structure which extends along a first direction, and a plurality of supporting patterns which are separated from each other and arranged along a second direction which is perpendicular to the first direction.

公开(公告)号：US12040354B2

公开(公告)日：2024-07-16

申请号：US18119009

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chu-Fu Lin ,  Chun-Hung Chen

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/91

Abstract: A capacitor structure comprises a substrate having a first side, a second side opposite to the first side and an upper surface corresponding to the first side; a plurality of first trenches formed on the first side of the substrate, disposed along a first direction and a second direction parallel to the upper surface, and penetrating the substrate along a third direction, the first direction, the second direction and the third direction orthogonal to each other; a plurality of second trenches formed on the second side of the substrate and penetrating the substrate along the third direction, the first trenches and the second trenches separated from each other in the first direction; a first capacitor extending along the first side and into the first trenches; and a second capacitor extending along the second side and into the second trenches.

公开(公告)号：US20240237335A9

公开(公告)日：2024-07-11

申请号：US17994009

申请日：2022-11-25

Applicant: United Microelectronics Corp.

Inventor： Yu-Jen Yeh

IPC: H01L29/76 ,  H01L29/423

CPC classification number: H01L27/11553 ,  H01L29/42328

Abstract: Provided are a flash memory and a manufacturing method thereof. The flash memory includes a floating gate disposed in a substrate, a first, a second and a third dielectric layers, a source region, a drain region, an erase gate on the second dielectric layer, and a select gate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the exposed surface of the floating gate. The source region is disposed in the substrate at one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate at another side of the floating gate and separated from the first dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

公开(公告)号：US20240234572A1

公开(公告)日：2024-07-11

申请号：US18108019

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang-An Huang ,  Ming-Hua Tsai ,  Wen-Fang Lee ,  Chin-Chia Kuo ,  Jung Han ,  Chun-Lin Chen ,  Ching-Chung Yang ,  Nien-Chung Li

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/7801

Abstract: An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.

公开(公告)号：US20240234539A9

公开(公告)日：2024-07-11

申请号：US18395657

申请日：2023-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.