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111.发明授权Method for the computer-aided generation of at least one part of an executable control program 有权用于计算机辅助生成可执行控制程序的至少一部分的方法公开(公告)号：US09250873B2
公开(公告)日：2016-02-02
申请号：US14024206
申请日：2013-09-11
Inventor： Karsten Fischer , Torsten Pietzsch , Michael Mair , Wolfgang Trautmann
IPC: G06F9/45 , G06F9/44 , G05B19/042
CPC classification number: G06F8/41 , G05B19/0426 , G06F8/34 , G06F8/35
Abstract: A method for the computer-aided generation of at least one part of an executable control program, particularly a measuring, control, regulating, and/or calibration program, for controlling a control system having at least one electronic processor unit is provided. The functionality of the control program is described at least partially in at least one graphical model and the graphical model is divided in hierarchical levels into submodels. A submodel can be divided nested into submodels of a lower hierarchical level, whereby values for options for the compiling of the graphical model to program code are preset and program code is generated from the model co-compiled to the executable control program. Values for options for the compiling of the graphical model to program code and to the executable control program can be preset thereby granularly with the automatic avoidance of conflicting presettings of values for these options.
Abstract translation: 提供了一种用于计算机辅助生成用于控制具有至少一个电子处理器单元的控制系统的可执行控制程序，特别是测量，控制，调节和/或校准程序的至少一部分的方法。 控制程序的功能至少部分地描述在至少一个图形模型中，并且图形模型被分层为子模型。 子模型可以被分成嵌套到较低层级的子模型，由此将用于将图形模型编译为程序代码的选项的值预先设置，并且从共同编译的模型生成程序代码到可执行控制程序。 可以将图形模型编译为程序代码和可执行控制程序的选项的值预先设置，从而通过自动避免这些选项的冲突预设值来进行细微预设。
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公开(公告)号：US20150347669A1
公开(公告)日：2015-12-03
申请号：US14823197
申请日：2015-08-11
Inventor： Heiko KALTE , Lukas FUNKE
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5027 , G06F17/5054
Abstract: A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.
Abstract translation: 一种在运行时改变FPGA信号值的方法，包括将具有至少一个信号值的FPGA硬件配置加载到FPGA上的步骤，在FPGA上运行FPGA硬件配置，设置传输到FPGA的信号值 从信号值确定回写数据，将写回数据作为状态数据写入FPGA的配置存储器，并将状态数据从配置存储器传送到FPGA的功能级别。 还提供了一种用于执行FPGA构建的方法，包括以下步骤：创建具有多个信号值的FPGA硬件配置，在FPGA硬件配置的相邻区域中布置信号值，确定用于状态数据的配置存储器的存储器位置 基于FPGA硬件配置的多个信号值，并创建包含信号值的列表。
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公开(公告)号：US20150324105A1
公开(公告)日：2015-11-12
申请号：US14702805
申请日：2015-05-04
Inventor： Sebastian SCHULTE
IPC: G06F3/0484 , G06F3/0482 , G06F17/30
CPC classification number: G06F3/04847 , G05B19/0426 , G05B2219/23067 , G06F3/0482 , G06F3/04842 , G06F17/30312
Abstract: A method and data processing system for linking a plurality of data structures of a data processing system with a plurality of elements of a man-machine interface (MMI) are provided. The method includes the steps: provision of an MMI with a plurality of elements, arranging a plurality of data structures in a list, selection of an element of the MMI by a user, automatic linking of a first data structure from the list with the selected element of the MMI, and setting the beginning of the list to the data structure that follows the previously linked data structure in the list. The steps of selection of an element of the MMI by a user, automatic linking of a first data structure from the list with the selected element of the MMI, and setting the beginning of the list to the data structure are carried out repeatedly.
Abstract translation: 提供了一种用于将数据处理系统的多个数据结构与人机界面（MMI）的多个元素相链接的方法和数据处理系统。 该方法包括以下步骤：提供具有多个元素的MMI，在列表中排列多个数据结构，由用户选择MMI的元素，将列表中的第一数据结构与所选择的自动链接 元素，并将列表的开头设置为列表中先前链接的数据结构之后的数据结构。 由用户选择MMI的元素，从列表中自动链接第一数据结构与MMI的所选元素以及将列表的开头设置为数据结构的步骤被重复执行。
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公开(公告)号：US09160338B2
公开(公告)日：2015-10-13
申请号：US14275284
申请日：2014-05-12
Inventor： Dirk Hasse , Robert Polnau
IPC: H03K19/173 , H03K19/177 , G06F7/38 , H03K19/0175 , G06F13/42
CPC classification number: H03K19/017509 , G06F13/4291 , H03K19/0175 , H03K19/17732 , H03K19/17744
Abstract: A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least one FPGA and the at least one I/O module, comprising the steps of configuring a maximum number of registers to be transmitted for each FPGA application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.
Abstract translation: 一种在至少一个FPGA与至少一个FPGA应用之间实现自适应接口的方法和被设计为相应的发送机侧或接收机侧的至少一个I / O模块，用于连接到FPGA，由此串行接口是 形成在所述至少一个FPGA和所述至少一个I / O模块之间，包括以下步骤：配置要针对每个FPGA应用发送的最大寄存器数量，为所有寄存器配置共享固定寄存器宽度，设置使能信号 在发送侧，要发送的寄存器的最大数量的寄存器发送，将发送端发送到接收端，并从发送方发送启用信号的寄存器 侧到接收机侧。
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公开(公告)号：US20140019942A1
公开(公告)日：2014-01-16
申请号：US13937691
申请日：2013-07-09
Inventor： Markus SUEVERN , Anne GEBURZI
IPC: G06F11/36
CPC classification number: G06F11/3664 , G06F11/3644 , G06F11/3688
Abstract: A development device and a method for creating and testing a control unit program, whereby the preparation of an intervention point for manipulating a quantity of a runtime environment for testing a control unit program component in a test environment having a test scenario program component and an observation device for receiving output values and indicating the test result. An executable program containing all program components is created from one or more program components, including a control unit program component that is to be tested and a test scenario program component. The creation includes generation of a runtime environment, wherein the runtime environment provides a communication channel for transmitting input and output values between the program components, and wherein a component test service is provided that offers an interface to the runtime environment pursuant to the AUTOSAR standard as an intervention point for manipulating a quantity of the runtime environment.
Abstract translation: 一种用于创建和测试控制单元程序的开发设备和方法，其中，在具有测试场景程序组件和观察的测试环境中，准备用于操纵用于测试控制单元程序组件的运行时环境的数量的介入点 用于接收输出值并指示测试结果的设备。 包含所有程序组件的可执行程序由一个或多个程序组件创建，包括要测试的控制单元程序组件和测试场景程序组件。 创建包括生成运行时环境，其中运行时环境提供用于在程序组件之间传送输入和输出值的通信通道，并且其中提供了组件测试服务，该组件测试服务根据AUTOSAR标准为运行时环境提供接口 用于操纵一定数量的运行时环境的干预点。
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Patent Agency Ranking
公开(公告)号：US11860301B2
公开(公告)日：2024-01-02
申请号：US17353905
申请日：2021-06-22
Inventor： Jeffrey Paul
IPC: G01S7/40
CPC classification number: G01S7/4065 , G01S7/4021 , G01S7/4069 , G01S7/4086
Abstract: A testing device for testing a distance sensor that operates using electromagnetic waves includes: a receiving element for receiving an electromagnetic free-space wave as a receive signal (SRX); and a radiating element for radiating an electromagnetic output signal (STX). In a test mode, a test signal unit generates a test signal (Stest), and the radiating element is configured to radiate the test signal (Stest) or a test signal (S′test) derived from the test signal (Stest) as the electromagnetic output signal (STX). In the test mode, an analysis unit is configured to analyze the receive signal (SRX) or the derived receive signal (S′RX) in terms of its phase angle (Phi) and/or amplitude (A) and store a determined value of phase angle (Phi) and/or amplitude (A) synchronously with the radiation of the test signal (Stest) or of the derived test signal (S′test) as the electromagnetic output signal (STX).
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117.发明授权公开(公告)号：US11843514B2
公开(公告)日：2023-12-12
申请号：US17518288
申请日：2021-11-03
Inventor： Heiko Kalte , Dominik Lubeley
CPC classification number: H04L41/145 , H04L41/12 , H04L43/50
Abstract: A computer-implemented method for restructuring a predefined distributed real-time simulation network, wherein the simulation network has a plurality of network nodes and a plurality of data connections, wherein each network node has at least one data connection interface for connecting a data connection, wherein the network nodes are at least partially in communication via the data connections, and wherein during operation of the simulation network a simulation application is executed on at least one network node. The method permits a structure for the real-time simulation network to be automatically found in which the critical communication connections are reduced and avoided as much as possible by determining the topology of the simulation network so that topology information concerning the network nodes and the data connections between the network nodes is available by determining expected values for node data rates or node latencies for the network nodes of the simulation network.
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公开(公告)号：US11699013B2
公开(公告)日：2023-07-11
申请号：US16012971
申请日：2018-06-20
Inventor： Axel Kiffe , Katrin Witting , Frank Puschmann
IPC: G06F30/367 , G05B13/04 , G05B17/02 , G06F30/20 , G06F111/10
CPC classification number: G06F30/367 , G05B13/04 , G05B17/02 , G06F30/20 , G06F2111/10
Abstract: A computer-implemented method for simulation of an electrical circuit with circuit components by at least one computing unit includes mapping a coupling of the substate representations in a coupling equation system for exchange of calculated coupling variables between the subcircuits. The method also includes calculating, in an evaluation step, at least one stability parameter on a basis of the coupling equation system, and deciding, in a selection step and depending on the at least one calculated stability parameter, whether the current separation of the electrical circuit into subcircuits will be used as the basis of the simulation. The method further includes performing, after a successful selection, the simulation of the electrical circuit by calculating the substate space representations on the at least one computing unit.
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公开(公告)号：US11663301B2
公开(公告)日：2023-05-30
申请号：US17400759
申请日：2021-08-12
Inventor： Matthias Nissen , Guido Schaefergockel
CPC classification number: G06F21/125 , G06F21/105
Abstract: A method for the usage-based licensing of one or more applications in a container, wherein the container comprises a license module, an application queries the presence of an application license via the license module and is only executed if an application license is present. In the license module, a linking of one or more application licenses with a unique identifier is stored, and the container comprises a settlement module, which retrieves a usage unit from an external license source. For the duration of an obtained usage unit, the settlement module provides the unique identifier in a secure data storage so that all applications linked with the unique identifier can be executed. A computer system and a computer program product are also provided.
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公开(公告)号：US11586793B2
公开(公告)日：2023-02-21
申请号：US16188893
申请日：2018-11-13
Inventor： Heiko Kalte , Dominik Lubeley
IPC: G06F30/331 , G06F30/34 , G06F30/327 , G06F9/30 , G06F11/36 , G06F30/333
Abstract: A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.
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