公开(公告)号：US06981067B2

公开(公告)日：2005-12-27

申请号：US10614863

申请日：2003-07-09

申请人： Yasuo Inoue

发明人： Yasuo Inoue

IPC分类号： G06F3/06 ,  G06F3/00 ,  G06F12/08 ,  G06F13/12 ,  G06F13/14 ,  G06F13/38 ,  G11C29/00

CPC分类号： G06F3/0601 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0689 ,  G06F12/0866 ,  G06F2003/0692 ,  G11C29/006 ,  H04L67/1097

摘要： A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

摘要翻译： 在位于主机（中央处理单元）和磁盘驱动器之间的盘控制器中提供多个独立高速缓存单元和非易失性存储器单元。 用于控制来自中央处理单元的数据传送的多个通道单元和用于控制与磁盘驱动器的数据传送的多个控制单元通过数据总线独立地连接到高速缓存单元和非易失性存储器单元 和接入线路。

公开(公告)号：US06981066B2

公开(公告)日：2005-12-27

申请号：US10614861

申请日：2003-07-09

申请人： Yasuo Inoue

发明人： Yasuo Inoue

IPC分类号： G06F3/06 ,  G06F3/00 ,  G06F12/08 ,  G06F13/12 ,  G06F13/14 ,  G06F13/38 ,  G11C29/00

CPC分类号： G06F3/0601 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0689 ,  G06F12/0866 ,  G06F2003/0692 ,  G11C29/006 ,  H04L67/1097

摘要： A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

公开(公告)号：US06737336B2

公开(公告)日：2004-05-18

申请号：US10183408

申请日：2002-06-28

申请人： Shuuichi Ueno ,  Yasuo Inoue ,  Masayoshi Shirahata

发明人： Shuuichi Ueno ,  Yasuo Inoue ,  Masayoshi Shirahata

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.

摘要翻译： 具有高绝缘特性的沟槽隔离结构的半导体器件以及半导体器件的制造方法适用于半导体器件的小型化，防止漏电流。 在要形成沟槽隔离结构的沟槽内的区域中，在半导体衬底和CVD氧化硅膜之间形成小密度多晶硅膜。 通过改变多晶硅膜的结晶结构来减轻在热处理期间在半导体衬底和CVD氧化硅膜之间产生的机械应力。

公开(公告)号：US06509583B1

公开(公告)日：2003-01-21

申请号：US09677848

申请日：2000-10-03

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L2904

CPC分类号： H01L21/76297 ,  H01L21/26586 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

公开(公告)号：US06235564B1

公开(公告)日：2001-05-22

申请号：US09487620

申请日：2000-01-20

申请人： Yasuyoshi Itoh ,  Yasuo Inoue ,  Hidekazu Oda

发明人： Yasuyoshi Itoh ,  Yasuo Inoue ,  Hidekazu Oda

IPC分类号： H01L21338

CPC分类号： H01L29/66545 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/1045 ,  H01L29/495 ,  H01L29/6659

摘要： A method of manufacturing a MISFET includes the steps of forming a gate insulation film (2) on a semiconductor substrate (1), forming a dummy gate (3B) made of a material having an etch selectivity relative to the material of the gate insulation film (2) on the gate insulation film (2), implanting an impurity into the semiconductor substrate (1), forming an interlayer insulation film (7), made of a material having an etch selectivity relative to the material of the dummy gate (3B) on a side surface of the dummy gate (3B), etching away the dummy gate (3B), and filling a space in which the dummy gate (3B) has been present with a gate electrode material of metal. Gradually thinning the dummy gate in the step of impurity implantation allows the formation of LDD regions and the patterning of a gate electrode below a minimum patterning size limit of a photolithographic technique. The method eliminates the need to take into consideration an etch selectivity between the gate electrode material and the gate insulation film material to manufacture an all-metal gate electrode.

摘要翻译： 一种制造MISFET的方法包括以下步骤：在半导体衬底（1）上形成栅极绝缘膜（2），形成由相对于栅极绝缘膜的材料具有蚀刻选择性的材料制成的虚拟栅极（3B） （2）在栅极绝缘膜（2）上，将杂质注入到半导体衬底（1）中，形成层间绝缘膜（7），其由具有相对于虚拟栅极（3B）的材料的蚀刻选择性的材料制成 ）在伪栅极（3B）的侧面上，蚀刻掉伪栅极（3B），并且填充其中存在虚拟栅极（3B）的空间与金属栅电极材料。 在杂质注入步骤中使虚拟栅极逐渐变薄，可以形成LDD区域，并使栅电极的图案化成为光刻技术的最小图案化尺寸极限。 该方法消除了考虑栅电极材料和栅极绝缘膜材料之间的蚀刻选择性以制造全金属栅电极的需要。

公开(公告)号：US6096583A

公开(公告)日：2000-08-01

申请号：US133690

申请日：1998-08-12

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/70

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78654

摘要： In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

摘要翻译： 在形成SOI衬底的硅半导体层中的元件隔离区域时，在形成于SOI层上的氧化物膜上沉积预定厚度的氮化硅膜。 以活性区域的设计尺寸对氮化硅膜进行构图，并且在图案化的氮化硅膜的侧表面上形成氮化硅膜的侧壁。 使用氮化物膜作为氧化掩模进行第一LOCOS工艺。 去除由第一LOCOS工艺形成的LOCOS膜，以在侧壁下形成更窄的凹面。 然后，沉积另一个氮化硅膜，并除去形成凹部的部分。 然后，进行第二LOCOS工艺以形成LOCOS膜作为元件隔离区。 第二LOCOS工艺使用具有窄腔的氧化掩模，使得有源区域和元件隔离区域的边界处的应力减小，并且可以抑制鸟喙的生长。

公开(公告)号：US6001635A

公开(公告)日：1999-12-14

申请号：US130929

申请日：1998-08-07

申请人： Yasuo Inoue ,  Sadako Inoue ,  Ken Kitajima

发明人： Yasuo Inoue ,  Sadako Inoue ,  Ken Kitajima

IPC分类号： C12N1/20 ,  C12N9/24 ,  C12P19/14 ,  C12R1/01

CPC分类号： C12Y302/01018 ,  C12N9/2402

摘要： A strain of Sphingobacterium multivorum, mOL12-4s, is disclosed which produces deaminoneuraminidase in high yields. The deaminoneuraminidase produced by mOL12-4s does not act on the ketosidic linkages of N-acetylneuraminic acid or N-glycolylneuraminic acid containing complex carbohydrates, but only on ketosidic linkages of deaminoneuraminic acid containing complex carbohydrates.

摘要翻译： 公开了一种以高产率产生脱氨基神经氨酸酶的多细胞鞘氨醇杆菌MOL12-4s的菌株。 由mOL12-4s产生的脱氨基神经氨酸酶不作用于含有复合碳水化合物的N-乙酰神经氨酸或N-羟乙酰神经氨酸的酮基键，而仅对含有复合碳水化合物的脱氨基神经氨酸的酮基键作用。

公开(公告)号：US5808341A

公开(公告)日：1998-09-15

申请号：US747933

申请日：1996-11-12

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

IPC分类号： H01L21/762 ,  H01L21/82 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L27/11807 ,  H01L27/1203 ,  H01L21/76281 ,  H01L21/76291

摘要： FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

摘要翻译： FS隔离场（10a，10b），LOCOS隔离场（11c，11d），FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i） 这个命令。 因此，可以提供主布局，其中将具有被提供固定电位的体的SOI晶体管和具有不具有固定电位的体的SOI晶体管混合。

公开(公告)号：US5514880A

公开(公告)日：1996-05-07

申请号：US142564

申请日：1993-10-28

申请人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

发明人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L29/78654 ,  H01L27/1281 ,  Y10S257/903

摘要： In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

摘要翻译： 在TFT负载型的小型化的完全CMOS SRAM中，场效应薄膜晶体管（TFT）能够实现对存储单元的稳定的读/写操作并且可以降低其功耗。 形成在绝缘体上的场效应薄膜晶体管包括有源层和栅电极。 栅电极形成在有源层的沟道区上，其间具有栅极绝缘膜。 有源层由沟道区和源极/漏极区形成。 沟道区由单晶硅层形成，不包含晶界。 源/漏区由多晶硅层形成。 沟道区域的晶体缺陷密度小于109个/ cm 2。 薄膜晶体管的通道宽度为1μm，导通电流为0.25μA/μm，OFF电流为15fA /μm。 薄膜晶体管可以被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。

公开(公告)号：US5096845A

公开(公告)日：1992-03-17

申请号：US496714

申请日：1990-03-21

申请人： Yasuo Inoue

发明人： Yasuo Inoue

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66787 ,  H01L21/8238 ,  H01L27/11807 ,  H01L29/0847 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/78 ,  H01L27/0928

摘要： A channel surface with a channel region and a gate electrode opposing to each other is formed approximately vertical to a main surface of a semiconductor substrate in the field effect transistor (FET). A p type (n type) single crystal silicon layer is formed in a hole of an insulating layer on the main surface of the substrate. N type (p type) drain and source regions are formed defining the channel region in the single crystal silicon layer. A gate electrode is formed above the channel region on the side wall of the single crystal silicon layer in the hole. The area of the main surface of the substrate occupied by one FET can be reduced in this manner. A semiconductor device can be provided in which FETs are integrated to a higher degree without degrading performance of the transistors. The method for manufacturing the semiconductor device comprises the steps of forming an insulating layer with a hole reaching to the main surface of the substrate, forming a single crystal silicon layer in the hole, forming a gate electrode on the side wall surface of the single crystal silicon layer, and forming source and drain regions in the single crystal silicon layer in selfalignment.