公开(公告)号：US5381235A

公开(公告)日：1995-01-10

申请号：US990460

申请日：1992-12-15

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： G01B11/24 ,  G01B11/02 ,  G01B11/25 ,  G01C3/06 ,  H01L27/14

CPC分类号： G01B11/024 ,  G01B11/2518

摘要： The present invention provides a three-dimensional shape measuring device and a sensor employed for the three-dimensional shape measuring device. The three-dimensional shape measuring device comprises a light source for scanning plane light over the surface of an object, an image sensor opposed to the object and provided with a plurality of pixels, an optical system for forming an image of a bright line appearing on the surface of the object due to plane light on the image sensor, a plurality of capacitors installed in association with pixels of the image sensor, a charger for storing given charges in a plurality of capacitors before plane light scanning starts, a plurality of dischargers lying in association with capacitors and gradually discharging the capacitors for pixels corresponding to a bright line image from when plane light scanning starts until the bright line image passes through the pixels, and an arithmetic logic means for computing charges remaining in the plurality of capacitors after plane light scanning is completed and thus providing a three-dimensional shape of an object. Thereby, a three-dimensional shape of an object can be measured at a high speed with high precision.

摘要翻译： 本发明提供了三维形状测量装置和用于三维形状测量装置的传感器。 三维形状测量装置包括：用于扫描物体表面上的平面光的光源，与该物体相对并设置有多个像素的图像传感器，用于形成亮线的图像的光学系统， 由于图像传感器上的平面光，物体的表面，与图像传感器的像素相关联地安装的多个电容器，用于在平面光扫描开始之前在多个电容器中存储给定电荷的充电器，多个放电器位于 与平面光扫描开始直到亮线图像通过像素的与亮线图像相对应的像素的电容器逐渐放电;以及算术逻辑装置，用于计算平面光后的多个电容器中剩余的电荷 扫描完成，从而提供对象的三维形状。 由此，可以高精度地测量物体的三维形状。

公开(公告)号：US5841171A

公开(公告)日：1998-11-24

申请号：US746951

申请日：1996-11-18

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78654

摘要： In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

摘要翻译： 在形成SOI衬底的硅半导体层中的元件隔离区域时，在形成于SOI层上的氧化物膜上沉积预定厚度的氮化硅膜。 以活性区域的设计尺寸对氮化硅膜进行构图，并且在图案化的氮化硅膜的侧表面上形成氮化硅膜的侧壁。 使用氮化物膜作为氧化掩模进行第一LOCOS工艺。 去除由第一LOCOS工艺形成的LOCOS膜，以在侧壁下形成更窄的凹面。 然后，沉积另一个氮化硅膜，并除去形成凹部的部分。 然后，进行第二LOCOS工艺以形成LOCOS膜作为元件隔离区。 第二LOCOS工艺使用具有窄腔的氧化掩模，使得有源区域和元件隔离区域的边界处的应力减小，并且可以抑制鸟喙的生长。

公开(公告)号：US5736438A

公开(公告)日：1998-04-07

申请号：US483411

申请日：1995-06-07

申请人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

发明人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L29/78654 ,  H01L27/1281 ,  Y10S257/903

摘要： In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

摘要翻译： 在TFT负载型的小型化的完全CMOS SRAM中，场效应薄膜晶体管（TFT）能够实现对存储单元的稳定的读/写操作并且可以降低其功耗。 形成在绝缘体上的场效应薄膜晶体管包括有源层和栅电极。 栅电极形成在有源层的沟道区上，其间具有栅极绝缘膜。 有源层由沟道区和源极/漏极区形成。 沟道区由单晶硅层形成，不包含晶界。 源/漏区由多晶硅层形成。 沟道区域的晶体缺陷密度小于109个/ cm 2。 薄膜晶体管的通道宽度为1μm，导通电流为0.25μA/μm，OFF电流为15fA /μm。 薄膜晶体管可以被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。

公开(公告)号：US6096583A

公开(公告)日：2000-08-01

申请号：US133690

申请日：1998-08-12

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/70

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78654

摘要： In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

摘要翻译： 在形成SOI衬底的硅半导体层中的元件隔离区域时，在形成于SOI层上的氧化物膜上沉积预定厚度的氮化硅膜。 以活性区域的设计尺寸对氮化硅膜进行构图，并且在图案化的氮化硅膜的侧表面上形成氮化硅膜的侧壁。 使用氮化物膜作为氧化掩模进行第一LOCOS工艺。 去除由第一LOCOS工艺形成的LOCOS膜，以在侧壁下形成更窄的凹面。 然后，沉积另一个氮化硅膜，并除去形成凹部的部分。 然后，进行第二LOCOS工艺以形成LOCOS膜作为元件隔离区。 第二LOCOS工艺使用具有窄腔的氧化掩模，使得有源区域和元件隔离区域的边界处的应力减小，并且可以抑制鸟喙的生长。

公开(公告)号：US5514880A

公开(公告)日：1996-05-07

申请号：US142564

申请日：1993-10-28

申请人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

发明人： Hisayuki Nishimura ,  Kazuyuki Sugahara ,  Shigenobu Maeda ,  Takashi Ipposhi ,  Yasuo Inoue ,  Toshiaki Iwamatsu ,  Mikio Ikeda ,  Tatsuya Kunikiyo ,  Junji Tateishi ,  Tadaharu Minato

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L27/11 ,  H01L27/1108 ,  H01L29/78654 ,  H01L27/1281 ,  Y10S257/903

摘要： In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.

摘要翻译： 在TFT负载型的小型化的完全CMOS SRAM中，场效应薄膜晶体管（TFT）能够实现对存储单元的稳定的读/写操作并且可以降低其功耗。 形成在绝缘体上的场效应薄膜晶体管包括有源层和栅电极。 栅电极形成在有源层的沟道区上，其间具有栅极绝缘膜。 有源层由沟道区和源极/漏极区形成。 沟道区由单晶硅层形成，不包含晶界。 源/漏区由多晶硅层形成。 沟道区域的晶体缺陷密度小于109个/ cm 2。 薄膜晶体管的通道宽度为1μm，导通电流为0.25μA/μm，OFF电流为15fA /μm。 薄膜晶体管可以被施加到用作CMOS型SRAM的存储单元中的负载晶体管的p沟道MOS晶体管。

公开(公告)号：US06727552B2

公开(公告)日：2004-04-27

申请号：US10062462

申请日：2002-02-05

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L2701

CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

公开(公告)号：US06649976B2

公开(公告)日：2003-11-18

申请号：US09982777

申请日：2001-10-22

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L2976

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/458 ,  H01L29/66507 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78621

摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

公开(公告)号：US6118154A

公开(公告)日：2000-09-12

申请号：US947345

申请日：1997-10-08

申请人： Yasuo Yamaguchi ,  Hirotoshi Sato ,  Yasuo Inoue ,  Toshiaki Iwamatsu

发明人： Yasuo Yamaguchi ,  Hirotoshi Sato ,  Yasuo Inoue ,  Toshiaki Iwamatsu

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/786 ,  H01L23/60

CPC分类号： H01L27/0251

摘要： An I/O protection circuit includes a P-channel MOS transistor connected between an input terminal and a power supply line, and an N-channel MOS transistor connected between the input terminal and a ground line. Gate electrodes of both the transistors are floated. The transistors may be replaced with gate diodes. Further, gate electrodes may be formed from the same layer as a gate electrode provided for field shielding.

摘要翻译： I / O保护电路包括连接在输入端和电源线之间的P沟道MOS晶体管和连接在输入端和接地线之间的N沟道MOS晶体管。 两个晶体管的栅极电极浮起来。 晶体管可以被栅极二极管代替。 此外，栅电极可以由与用于场屏蔽的栅电极相同的层形成。

公开(公告)号：US6051494A

公开(公告)日：2000-04-18

申请号：US855259

申请日：1997-05-13

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Yasuo Yamaguchi ,  Tadashi Nishimura

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/84 ,  H01L27/12 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L21/26506 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/458 ,  H01L29/66507 ,  H01L29/66659 ,  H01L29/66772 ,  H01L21/26586 ,  H01L29/78621

摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

摘要翻译： 可以获得其中源极/漏极区域的寄生电阻可以比漏极区域的寄生电阻降低的半导体器件及其制造方法。 在半导体装置中，仅将钝化离子注入到半导体层的源极区域，以损坏半导体层的表面附近的晶体，从而促进了硅化反应。 因此，在源极区域中，可以形成更厚的硅化钛膜。

公开(公告)号：US5656537A

公开(公告)日：1997-08-12

申请号：US463253

申请日：1995-06-05

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue

IPC分类号： H01L21/32 ,  H01L21/322 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/32 ,  H01L21/3226 ,  H01L21/76264 ,  H01L29/786 ,  H01L29/78609 ,  H01L29/78618 ,  H01L21/76281

摘要： A buried oxide film and an SOI layer are formed on the main surface of a substrate. A nitride film patterned in predetermined configuration is formed on the surface of the SOI layer. The first selective oxidation treatment is applied to the SOI layer with the nitride film used as a mask. At this stage, the isolating oxide film is formed not to reach the buried oxide film. Anisotropic etching is applied to the isolating oxide film with the nitride film used as a mask. A sidewall insulating layer of oxidation-resistant material is formed on the sidewall of the nitride film. With the sidewall insulating layer and nitride film used as masks, the second selective oxidation treatment is applied to the SOI layer, thereby forming an isolating oxide film. Thereby, it becomes possible to prevent a parasitic MOS transistor being formed in the end of the SOI layer.

摘要翻译： 在衬底的主表面上形成掩埋氧化膜和SOI层。 在SOI层的表面上形成以规定构造形成图案的氮化膜。 将第一选择性氧化处理施加到具有用作掩模的氮化物膜的SOI层。 在这个阶段，隔离氧化膜形成为不到达掩埋氧化膜。 使用用作掩模的氮化物膜对隔离氧化膜施加各向异性蚀刻。 在氮化膜的侧壁上形成耐氧化材料的侧壁绝缘层。 利用侧壁绝缘层和氮化物膜作为掩模，对SOI层施加第二选择性氧化处理，从而形成隔离氧化膜。 由此，能够防止在SOI层的端部形成寄生MOS晶体管。