公开(公告)号：US20220093647A1

公开(公告)日：2022-03-24

申请号：US17030226

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20210408284A1

公开(公告)日：2021-12-30

申请号：US16912136

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Ashish AGRAWAL ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Koustav GANGULY ,  Ryan KEECH ,  Siddharth CHOUKSEY ,  Willy RACHMADY

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165

Abstract: Gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, and methods of fabricating gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, are described. For example, an integrated circuit structure includes an insulator layer above a substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator layer. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and on the insulator layer. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires. The gate stack includes a high-k dielectric layer continuous with and having a same composition as the insulator layer.

公开(公告)号：US20210408283A1

公开(公告)日：2021-12-30

申请号：US16912127

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Ashish AGRAWAL ,  Anand S. MURTHY ,  Cory BOMBERGER ,  Jack T. KAVALIEROS ,  Koustav GANGULY ,  Ryan KEECH ,  Siddharth CHOUKSEY ,  Susmita GHOSE ,  Willy RACHMADY

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/165

Abstract: Gate-all-around integrated circuit structures having strained source or drain structures on an insulator layer, and methods of fabricating gate-all-around integrated circuit structures having strained source or drain structures on an insulator layer, are described. For example, an integrated circuit structure includes an insulator layer above a substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator layer. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is on the insulator layer. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and on the insulator layer. Each of the pair of epitaxial source or drain structures has a compressed or an expanded lattice.

公开(公告)号：US20210408239A1

公开(公告)日：2021-12-30

申请号：US16913848

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Ashish AGRAWAL ,  Seung Hoon SUNG ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Willy RACHMADY ,  Jessica TORRES ,  Martin M. MITAN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/088

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of semiconductor channels with a first end and second end. In an embodiment, individual ones of the semiconductor channels comprise a nitrided surface. In an embodiment, the semiconductor device further comprises a source region at the first end of the stack and a drain region at the second end of the stack. In an embodiment, a gate dielectric surrounds the semiconductor channels, and a gate electrode surrounding the gate dielectric.

公开(公告)号：US20200343379A1

公开(公告)日：2020-10-29

申请号：US16634517

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY ,  Shriram SHIVARAMAN ,  Inanc MERIC ,  Benjamin CHU-KUNG

IPC: H01L29/786 ,  H01L29/51 ,  H01L27/108 ,  H01L27/24 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200312973A1

公开(公告)日：2020-10-01

申请号：US16651955

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Benjamin CHU-KUNG ,  Shriram SHIVARAMAN

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: This disclosure illustrates a transistor with dual gate workfunctions. The transistor with dual gate workfunctions may comprise a source region, a drain region, a channel between the source region and the drain region, and a gate to control a conductivity of the channel. The gate may comprise a first portion with a first workfunction and a second portion with a second workfunction. One of the portions is nearer the source region than the other portion. The workfunction of the portion nearer the source provides a lower thermionic barrier than the workfunction of the portion further away from the source.

公开(公告)号：US20200227568A1

公开(公告)日：2020-07-16

申请号：US16638301

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Van H. LE ,  Abhishek A. SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Ravi PILLARISETTY ,  Miriam R. RESHOTKO ,  Shriram SHIVARAMAN ,  Li Huey TAN ,  Tristan A. TRONIC ,  Jack T. KAVALIEROS

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/40

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200066912A1

公开(公告)日：2020-02-27

申请号：US16325164

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Van H. LE ,  Rafael RIOS ,  Shriram SHIVARAMAN ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC

IPC: H01L29/786 ,  H01L29/221 ,  H01L29/66

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors. For instance, there is disclosed in accordance with one embodiment a semiconductor device having therein a substrate; a bi-layer oxides layer formed from a first oxide material and a second oxide material, the first oxide material comprising a semiconducting oxide material and having different material properties from the second oxide material comprising a high mobility oxide material; a channel layer formed atop the substrate, the channel layer formed from the semiconducting oxide material of the bi-layer oxides layer; a high mobility oxide layer formed atop the channel layer, the high conductivity oxide layer formed from the high mobility oxide material of the bi-layer oxides layer; metallic contacts formed atop the high mobility oxide layer; a gate and a gate oxide material formed atop the high mobility oxide layer, the gate oxide material being in direct contact with the high mobility oxide layer; and spacers separating the metallic contacts from the gate and gate oxide material. Other related embodiments are disclosed.

公开(公告)号：US20190393267A1

公开(公告)日：2019-12-26

申请号：US16480598

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Van H. LE ,  Gilbert DEWEY ,  Jack T. KAVALIEROS

IPC: H01L27/24 ,  H01L27/108 ,  H01L27/22 ,  H01L29/78 ,  H01L29/66 ,  H01L43/12 ,  H01L45/00

Abstract: A programmable array including a plurality of cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, the transistor including a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region and includes a width dimension equivalent to a width dimension of the body of the transistor. A method of forming an integrated circuit including forming bodies in a plurality rows on a substrate, each of the bodies including a programmable element and a first diffusion region, a second diffusion region and a channel of a transistor; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material; and replacing the masking material with an address line material.

公开(公告)号：US20190304897A1

公开(公告)日：2019-10-03

申请号：US15943565

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Abhishek SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532 ,  H01L27/108

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.