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公开(公告)号：US11742275B2
公开(公告)日：2023-08-29
申请号：US17566523
申请日：2021-12-30
Applicant: Intel Corporation
Inventor： Zhiguo Qian , Kemal Aygun , Yu Zhang
IPC: H01L23/498 , H01L21/48
CPC classification number: H01L23/49827 , H01L23/49816 , H01L23/49838 , H01L21/486 , H01L2924/0002 , H01L2924/0002 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
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公开(公告)号：US11715889B2
公开(公告)日：2023-08-01
申请号：US17402916
申请日：2021-08-16
Applicant: Intel Corporation
Inventor： Zhichao Zhang , Jiwei Sun , Kemal Aygun
CPC classification number: H01Q21/24 , H05K1/0243 , H05K1/0248 , H01P9/00 , H05K2201/10098
Abstract: Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase.
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113.发明申请公开(公告)号：US20220407254A1
公开(公告)日：2022-12-22
申请号：US17352103
申请日：2021-06-18
Applicant: Intel Corporation
Inventor： Zhichao Zhang , Zhe Chen , Steven A. Klein , Feifei Cheng , Srikant Nekkanty , Kemal Aygun , Michael E. Ryan , Pooya Tadayon
Abstract: A microelectronic socket structure and a method of forming the same. The socket structure comprises: a socket structure housing defining a cavity therein; and an interconnection structure including: a contact element disposed at least in part within the cavity, and configured to be electrically coupled to a corresponding microelectronic package, the contact element corresponding to one of a signal contact element or a ground contact element; and a conductive structure disposed at least in part within the cavity, electrically coupled to the contact element, and having an outer contour that is non-conformal with respect to an outer contour of the contact element.
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公开(公告)号：US11291133B2
公开(公告)日：2022-03-29
申请号：US15938980
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Zhichao Zhang , Gregorio R. Murtagian , Kuang C Liu , Kemal Aygun
Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
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公开(公告)号：US20210167015A1
公开(公告)日：2021-06-03
申请号：US17114954
申请日：2020-12-08
Applicant: Intel Corporation
Inventor： Zhiguo Qian , Kemal Aygun
IPC: H01L23/538 , H01L23/00 , H01L23/522 , H01L23/528
Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
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Patent Agency Ranking
公开(公告)号：US10950550B2
公开(公告)日：2021-03-16
申请号：US15774306
申请日：2015-12-22
Applicant: Intel Corporation
Inventor： Zhiguo Qian , Jianyong Xie , Kemal Aygun
IPC: H01L23/12 , H01L23/14 , H01L23/48 , H01L21/4763 , H01L23/538 , H01L21/48 , H01L23/498 , H01L23/00 , H01L25/065
Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.
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公开(公告)号：US20210057321A1
公开(公告)日：2021-02-25
申请号：US17074820
申请日：2020-10-20
Applicant: Intel Corporation
Inventor： Zhiguo Qian , Kemal Aygun , Yu Zhang
IPC: H01L23/498
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
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公开(公告)号：US10886171B2
公开(公告)日：2021-01-05
申请号：US16098662
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Yu Amos Zhang , Kemal Aygun
IPC: H01L21/768 , H01L23/522 , H01L23/50
Abstract: Integrated circuit (IC) chip “on-die” interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) “last silicon metal level (LSML)” data signal “leadway (LDW) routing” traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.
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公开(公告)号：US10804650B2
公开(公告)日：2020-10-13
申请号：US16468271
申请日：2016-12-31
Applicant: Intel Corporation
Inventor： Jeffrey Lee , Brent R. Rothermel , Kemal Aygun
IPC: H01R12/00 , H01R13/6471 , H01R13/6587 , H01R43/20
Abstract: Electrical connector technology is disclosed. In one example, a connector for coupling an electronics sub-assembly to an electronics assembly comprises a connector body having and a sub-assembly interface configured to electrically couple to an electronics sub-assembly. The connector has a circuit board interface configured to electrically couple to a circuit board of an electronics assembly. The connector has at least two rows of contacts configured to electrically couple the circuit board to the electronics sub-assembly. The at least two rows of contacts are aligned offset relative to each other such that any ground contact of one row avoids intersection of a plane in which any ground contact of the other row resides to at least partially cancel row-to-row crosstalk when the at least two rows of contacts are transmitting signals at a predetermined high-speed bit rate.
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公开(公告)号：US20200107463A1
公开(公告)日：2020-04-02
申请号：US16146908
申请日：2018-09-28
Applicant: Intel Corporation
Inventor： Srikant Nekkanty , Zhichao Zhang , Kemal Aygun
Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.
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