公开(公告)号：US09692147B1

公开(公告)日：2017-06-27

申请号：US14979037

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Donald T. Tran ,  Gregorio R. Murtagian

IPC: H01R4/48 ,  H01R43/16 ,  H05K5/00 ,  H01R13/73

CPC classification number: H01R4/58 ,  H01R12/52 ,  H01R12/718 ,  H01R12/73 ,  H05K5/0086

Abstract: An electronic device connection system includes a first electrical device and a second electrical device. The first electrical device includes a plurality of electrical connectors disposed in, on, or about at least a portion of an exterior surface of the first electrical device. The second electrical device includes a plurality of electrical contacts disposed in, on, or about at least a portion of an exterior surface of the second electrical device. A mechanical compressor exerts a force on at least one of the first electrical device or the second electrical device such that the electrical connections on the first electrical device physically and conductively couple to the electrical contacts on the second electrical device. The device casing may function as the mechanical compressor. The electrical connectors and/or electrical contacts may include injection molded connectors that include a conductive material dispersed in a thermoplastic matrix.

公开(公告)号：US12174436B2

公开(公告)日：2024-12-24

申请号：US17214035

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Wesley Morgan ,  Srikant Nekkanty ,  Todd R. Coons ,  Gregorio R. Murtagian ,  Xiaoqian Li ,  Nitin Deshpande ,  Divya Pratap

IPC: H04B10/00 ,  G02B6/42

Abstract: Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.

公开(公告)号：US20200335432A1

公开(公告)日：2020-10-22

申请号：US16388136

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Gregorio R. Murtagian ,  Jeffory L. Smalley ,  Thomas T. Holden ,  Silver A. Estrada Rodriguez ,  Luis E. Rosales Galvan

IPC: H01L23/498 ,  H01L21/67 ,  H05K1/18

Abstract: A circuit board assembly includes at least one circuit board having a plurality of conductive layers, the at least one circuit board having a first face and an opposite second face. A first chip socket on the first face is positioned opposite of a second chip socket on the second face. In one example, each chip socket can receive a processor. The first and second chip sockets may be arranged in a mirrored fashion with respect to one another, or an overlapping but non-mirrored fashion. In any such arrangements, as fasteners are tightened to fully seat first and second chips respectively installed in the first and second chip sockets, forces applied to the first chip effectively neutralize or otherwise reduce opposing forces applied to the second chip, thereby reducing circuit board deflection.

公开(公告)号：US09461431B2

公开(公告)日：2016-10-04

申请号：US14751871

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Gregorio R. Murtagian ,  Bhanu Jaiswal ,  Sriram Srinivasan ,  Michael J. Hill

IPC: H01R11/30 ,  H01R43/20 ,  H01R13/62 ,  H01R43/26 ,  H01R12/73

CPC classification number: H01R43/205 ,  H01R12/73 ,  H01R13/6205 ,  H01R43/26 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49149

Abstract: A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands.

公开(公告)号：US12207398B2

公开(公告)日：2025-01-21

申请号：US17664408

申请日：2022-05-21

Applicant: Georgia Tech Research Corporation ,  Intel Corporation

Inventor： Omkar Gupte ,  Vanessa Smet ,  Gregorio R. Murtagian

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/22

Abstract: An electronic device carrier structure can include a substrate including a plurality of electrical contacts spaced apart on the substrate, a plurality of electrically conductive balls, each of the electrically conductive balls being on a respective one of the plurality of electrical contacts, solder attaching each of the electrically conductive balls to respective ones of the electrical contacts to form an attachment boundary where the solder ends on a surface of each of the plurality of electrically conductive balls, and a polymer layer extending on the substrate onto the plurality of electrically conductive balls to form a surface of the polymer layer at a contact point on the plurality of electrically conductive balls that is above the attachment boundary and below an apex of each of the plurality of electrically conductive balls.

公开(公告)号：US20220386457A1

公开(公告)日：2022-12-01

申请号：US17664408

申请日：2022-05-21

Applicant: Georgia Tech Research Corporation ,  Intel Corporation

Inventor： Omkar Gupte ,  Vanessa Smet ,  Gregorio R. Murtagian

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/22

Abstract: An electronic device carrier structure can include a substrate including a plurality of electrical contacts spaced apart on the substrate, a plurality of electrically conductive balls, each of the electrically conductive balls being on a respective one of the plurality of electrical contacts, solder attaching each of the electrically conductive balls to respective ones of the electrical contacts to form an attachment boundary where the solder ends on a surface of each of the plurality of electrically conductive balls, and a polymer layer extending on the substrate onto the plurality of electrically conductive balls to form a surface of the polymer layer at a contact point on the plurality of electrically conductive balls that is above the attachment boundary and below an apex of each of the plurality of electrically conductive balls.

公开(公告)号：US11291133B2

公开(公告)日：2022-03-29

申请号：US15938980

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Gregorio R. Murtagian ,  Kuang C Liu ,  Kemal Aygun

IPC: H05K7/10 ,  H05K1/11 ,  H05K1/02 ,  H01R13/24

Abstract: Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.

公开(公告)号：US10396036B2

公开(公告)日：2019-08-27

申请号：US15774257

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos Zhang ,  Zhiguo Qian ,  Kemal Aygun ,  Yidnekachew S. Mekonnen ,  Gregorio R. Murtagian ,  Sanka Ganesan ,  Eduard Roytman ,  Jeff C. Morriss

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065

Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.

公开(公告)号：US09832876B2

公开(公告)日：2017-11-28

申请号：US14575775

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

公开(公告)号：US20150155092A1

公开(公告)日：2015-06-04

申请号：US14616508

申请日：2015-02-06

Applicant: Intel Corporation

Inventor： Gregorio R. Murtagian ,  Robert L. Sankman ,  Brent S. Stone ,  Kaladhar Radhakrishnan ,  Joshua D. Heppner

IPC: H01F27/28 ,  H01F27/06 ,  H01F27/02

CPC classification number: H01F27/2852 ,  H01F17/045 ,  H01F27/02 ,  H01F27/027 ,  H01F27/06 ,  H01F27/2847 ,  H01F27/292 ,  H01F2027/065 ,  H01F2027/297 ,  H01L2224/16225 ,  H01L2924/181 ,  Y10T29/4902 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed towards an inductor structure having one or more strips of conductive material disposed around a core. The strips may have contacts at a first end and a second end of the strips, and may be disposed around the core with a gap between the contacts. The inductor structure may be mounted on a surface of a substrate, and one or more traces may be formed in the surface of the substrate to electrically couple two or more of the strips of conductive material to one another to form inductive coils. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有围绕芯设置的一个或多个导电材料条的电感器结构。 条带可以在条的第一端和第二端处具有触点，并且可以在接触件之间具有间隙而围绕芯设置。 电感器结构可以安装在衬底的表面上，并且可以在衬底的表面中形成一个或多个迹线，以将两个或更多个导电材料条彼此电耦合以形成感应线圈。 可以描述和/或要求保护其他实施例。