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    Stacked Vertical Transistor-Based Mask-Programmable ROM
    113.
    发明申请
    Stacked Vertical Transistor-Based Mask-Programmable ROM 审中-公开

    公开(公告)号：US20200035691A1

    公开(公告)日：2020-01-30

    申请号：US16590199

    申请日：2019-10-01

    Applicant: International Business Machines Corporation

    Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Tak Ning ,  Bahman Hekmatshoartabari

    IPC: H01L27/112 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

    Abstract: VFET-based mask-programmable ROM are provided. In one aspect, a method of forming a ROM device includes: forming a bottom drain on a wafer; forming fins on the bottom drain with a top portion having a channel dopant at a different concentration than a bottom portion of the fins; forming bottom/top dummy gates alongside the bottom/top portions of the fins; forming a source in between the bottom/top dummy gates; forming a top drain above the top dummy gates; removing the bottom/top dummy gates; and replacing the bottom/top dummy gates with bottom/top replacement gates, wherein the bottom drain, the bottom replacement gates, the bottom portion of the fins, and the source form bottom VFETs of the ROM device, and wherein the source, the top replacement gates, the top portion of the fins, and the top drain form top VFETs stacked on the bottom VFETs. A ROM device is also provided.

    STACKED FINFET EEPROM
    117.
    发明申请
    STACKED FINFET EEPROM 审中-公开

    公开(公告)号：US20190164980A1

    公开(公告)日：2019-05-30

    申请号：US15825678

    申请日：2017-11-29

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

    IPC: H01L27/11521 ,  H01L29/78 ,  G11C16/04 ,  H01L27/11568 ,  H01L27/12 ,  H01L27/092 ,  H01L27/112 ,  H01L27/06

    Abstract: A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.

    Method of making thin SRAM cell having vertical transistors
    118.
    发明授权
    Method of making thin SRAM cell having vertical transistors 有权

    公开(公告)号：US10297512B2

    公开(公告)日：2019-05-21

    申请号：US15810654

    申请日：2017-11-13

    Applicant: International Business Machines Corporation

    Inventor： Karthik Balakrishnan ,  Michael A. Guillorn ,  Pouya Hashemi ,  Alexander Reznicek

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/06 ,  H01L27/06 ,  H01L29/786 ,  H01L21/84 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/41 ,  H01L29/775

    Abstract: A memory device includes six field effect transistors (FETs) formed with semiconductor nanowires arranged on a substrate in an orientation substantially perpendicular to the substrate. The semiconductor nanowires have bottom contacts, gate contacts separated in a direction perpendicular to the substrate from the bottom contacts, and top contacts separated in a direction perpendicular to the substrate from the gate contacts. The necessary connections are made among the bottom, gate, and top contacts to form the memory device using first, second, and third metallization layers, the first metallization layer being separated in a direction perpendicular to the substrate from the top contacts, the second metallization layer being separated in a direction perpendicular to the substrate from the first metallization layer, and the third metallization layer being separated in a direction perpendicular to the substrate from the second metallization layer. Vias connect the various contacts to the overlying metallization layers as necessary. A method for forming the memory device is also outlined.

    Strained stacked nanowire field-effect transistors (FETs)
    120.
    发明授权
    Strained stacked nanowire field-effect transistors (FETs) 有权

    公开(公告)号：US10229996B2

    公开(公告)日：2019-03-12

    申请号：US15583283

    申请日：2017-05-01

    Applicant: International Business Machines Corporation

    Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/02 ,  H01L21/02 ,  H01L21/311 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775

    Abstract: A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained SiGe layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained SiGe layers are anchored to one another and a compressive strain is maintained in each of the compressively strained SiGe layers.

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