公开(公告)号：US09092330B2

公开(公告)日：2015-07-28

申请号：US13834959

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Glenn D. Gilda ,  Mark R. Hodges ,  Vesselina K. Papazova ,  Patrick J. Meaney

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/08

CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F11/08

Abstract: Embodiments relate to early data delivery prior to error detection completion in a memory system. One aspect is a system that includes a cache subsystem interface with a correction pipeline in a system domain. The system includes a memory control unit interface in a memory controller nest domain and a buffer control block providing an asynchronous boundary layer between the system domain and the memory controller nest domain. A controller is configured to receive a frame of a multi-frame data block and write the frame to the buffer control block. The frame is read by the cache subsystem interface prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to the correction pipeline in the system domain.

Abstract translation: 实施例涉及在存储器系统中的错误检测完成之前的早期数据传送。 一个方面是包括具有系统域中的校正流水线的缓存子系统接口的系统。 该系统包括存储器控制器嵌套域中的存储器控​​制单元接口和在系统域和存储器控制器嵌套域之间提供异步边界层的缓冲器控制块。 控制器被配置为接收多帧数据块的帧并将该帧写入缓冲器控制块。 在完成多帧数据块的错误检测之前，该帧由高速缓存子系统接口读取。 对存储器控制器嵌套域中的帧执行错误检测。 基于检测到帧中的错误，拦截信号从存储器控制器嵌套域发送到系统域中的校正流水线。

公开(公告)号：US09086990B2

公开(公告)日：2015-07-21

申请号：US13788744

申请日：2013-03-07

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/10 ,  G06F11/08 ,  G06F11/07 ,  G11C29/12

CPC classification number: G06F11/1064 ,  G06F11/073 ,  G06F11/076 ,  G06F11/08 ,  G11C2029/1204

Abstract: Embodiments relate to a computer system for bitline deletion, the system including a cache controller and cache. The system is configured to perform a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line, recording a second address of the second error, comparing first and second bitline addresses, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to the third bitline address and deleting a location corresponding to the third cache line based on the activated bitline delete mode and matching third and second bitline addresses.

Abstract translation: 实施例涉及用于位线删除的计算机系统，该系统包括高速缓存控制器和高速缓存。 该系统被配置为执行一种方法，包括当读取第一高速缓存线时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误，记录第二错误的第二地址，比较 第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三高速缓存线时检测第三错误，记录第三位线地址 将第二位线地址与第三位线地址进行比较，并且基于激活的位线删​​除模式和匹配的第三和第二位线地址来删除与第三高速缓存线对应的位置。

公开(公告)号：US20140281783A1

公开(公告)日：2014-09-18

申请号：US13835444

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark R. Hodges ,  Irving G. Baysah ,  John S. Dodson ,  Patrick J. Meaney ,  Glenn D. Gilda

IPC: H04L1/18 ,  G06F11/16

CPC classification number: H04L1/1874 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/141 ,  G06F11/1625 ,  G11C7/1066 ,  G11C2211/4061 ,  H04L1/188

Abstract: Embodiments relate to replay suspension in a memory system. One aspect is a system that includes a replay buffer coupled to a memory controller interface, and a replay control coupled to the replay buffer and a memory controller. The replay control is configured to receive an error indication associated with sending data from the memory controller interface to a memory subsystem as part of an operation. A replay pending signal is provided to the memory controller based on the error indication. Based on waiting for a period of time sufficient for the memory controller to provide remaining data associated with the operation to the replay buffer, a replay signal is asserted.

Abstract translation: 实施例涉及在存储器系统中的重放暂停。 一个方面是包括耦合到存储器控制器接口的重放缓冲器和耦合到重放缓冲器的重放控制器和存储器控制器的系统。 重播控制被配置为接收与作为操作的一部分的从存储器控制器接口发送数据到存储器子系统相关联的错误指示。 基于错误指示将重放等待信号提供给存储器控制器。 基于等待一段足以使存储器控制器向重播缓冲器提供与该操作相关联的剩余数据的时间段，断言重放信号。

公开(公告)号：US20140281325A1

公开(公告)日：2014-09-18

申请号：US13835485

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Patrick J. Meaney ,  Glenn D. Gilda ,  Eric E. Retter ,  John S. Dodson ,  Gary A. Van Huben ,  Brad W. Michael ,  Stephen J. Powell

IPC: G11C7/22

CPC classification number: G06F11/1679 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F1/32 ,  G06F11/1497 ,  G06F11/1604 ,  G06F11/1675 ,  G06F13/1689 ,  G06F13/1694 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/52

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract translation: 实施例涉及存储器系统中的失步检测和失序检测。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。 存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。 存储器控制单元基于每个通道的偏斜值来调整定时对准。 比较每个定时调整的总结输入。 基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。

公开(公告)号：US08775858B2

公开(公告)日：2014-07-08

申请号：US13793363

申请日：2013-03-11

Applicant: International Business Machines Corporation

Inventor： Kevin C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  Eldee Stephens

IPC: G06F11/00

CPC classification number: G06F11/2053 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1004 ,  G06F11/108 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2007 ,  G06F2211/1088

Abstract: Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing based on the removing any stale data being complete.

Abstract translation: 在包括存储器控制器，与存储器控制器通信的多个存储器通道，配置用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供异构恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于在其他存储器通道执行正常的系统操作时对故障存储器通道执行恢复操作，以使恢复的通道与其它存储器通道重新进入操作模式， 存储操作，用于继续标记恢复的通道以防止陈旧的数据，用于在恢复操作完成之后去除任何陈旧的数据，以及用于去除恢复的通道上的标记，以允许所有存储器通道的正常系统操作， 基于删除任何陈旧的数据完成删除。

公开(公告)号：US08769335B2

公开(公告)日：2014-07-01

申请号：US13792933

申请日：2013-03-11

Applicant: International Business Machines Corporation

Inventor： Kevin C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  Eldee Stephens

IPC: G06F11/00

CPC classification number: G06F11/1666 ,  G06F11/1044 ,  G06F11/108 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/20 ,  G06F11/2007 ,  G06F2211/1088

Abstract: A computer implemented method for providing homogeneous recovery in a redundant memory system. The method includes receiving a notification that a memory channel has failed, where the memory channel is one of a plurality of memory channels in a memory system. New operations are blocked from starting on the memory channels in response to the notification, and any pending operations on the memory channels are completed in response to the notification. A recovery operation is performed on the memory channels in response to the completing. The new operations are started on at least a first subset of the memory channels in response to the recovery operation completing. The memory system is configured to operate with the first subset of the memory channels.

Abstract translation: 一种用于在冗余存储器系统中提供均匀恢复的计算机实现的方法。 该方法包括接收存储器通道已经失败的通知，其中存储器通道是存储器系统中的多个存储器通道之一。 响应于通知，新的操作被阻止在内存通道上启动，响应于该通知，内存通道上的任何未完成的操作都被完成。 响应于完成，对存储器通道进行恢复操作。 响应于恢复操作完成，至少在存储器通道的第一子集上开始新的操作。 存储器系统被配置为与存储器通道的第一子集一起操作。