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公开(公告)号：US10304560B2
公开(公告)日：2019-05-28
申请号：US15255368
申请日：2016-09-02
IPC分类号： G11C29/00 , G06F11/10 , G06F12/1009 , G06F12/0871 , G06F3/06
摘要： Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.
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公开(公告)号：US20160188423A1
公开(公告)日：2016-06-30
申请号：US15073699
申请日：2016-03-18
发明人： Patrick J. Meaney , Glenn D. Gilda , Eric E. Retter , John S. Dodson , Gary A. Van Huben , Brad W. Michael , Stephen J. Powell
CPC分类号： G06F11/1679 , G06F1/04 , G06F1/10 , G06F1/12 , G06F1/32 , G06F11/1497 , G06F11/1604 , G06F11/1675 , G06F13/1689 , G06F13/1694 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/4076 , G11C11/4093 , G11C29/52
摘要： Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.
摘要翻译： 实施例涉及存储器系统中的失步检测和失序检测。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。 存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。 存储器控制单元基于每个通道的偏斜值来调整定时对准。 比较每个定时调整的总结输入。 基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。
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公开(公告)号：US10824504B2
公开(公告)日：2020-11-03
申请号：US15953805
申请日：2018-04-16
发明人： James A. O'Connor, Jr. , Barry M. Trager , Warren E. Maule , Marc A. Gollub , Brad W. Michael , Patrick J. Meaney
摘要： Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
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公开(公告)号：US10297335B2
公开(公告)日：2019-05-21
申请号：US15255324
申请日：2016-09-02
摘要： Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.
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公开(公告)号：US10140186B2
公开(公告)日：2018-11-27
申请号：US15806404
申请日：2017-11-08
IPC分类号： G06F11/00 , G06F11/14 , G06F11/07 , G06F12/128 , G06F12/0871 , G06F12/0804 , G06F12/12
摘要： An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.
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公开(公告)号：US20170123936A1
公开(公告)日：2017-05-04
申请号：US14929505
申请日：2015-11-02
CPC分类号： G06F11/1451 , G06F11/0787 , G06F11/1435 , G06F12/0804 , G06F12/0871 , G06F12/12 , G06F12/128 , G06F2201/84 , G06F2212/604 , G06F2212/621 , G06F2212/70
摘要： An aspect includes memory error recovery in a memory system includes detecting an error condition within a memory chip of the memory system. A chip mark is applied to the memory chip to flag the error condition. An address range of the memory chip associated with the error condition is determined. Data are written from the address range of the memory chip to a cache memory. The chip mark is removed based on determining that all of the data from the address range have been written to the cache memory.
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公开(公告)号：US11017875B2
公开(公告)日：2021-05-25
申请号：US16363110
申请日：2019-03-25
摘要： Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.
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公开(公告)号：US10971246B2
公开(公告)日：2021-04-06
申请号：US16387846
申请日：2019-04-18
IPC分类号： G11C29/00 , G06F11/10 , G06F12/1009 , G06F12/0871 , G06F3/06
摘要： Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.
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公开(公告)号：US20190317856A1
公开(公告)日：2019-10-17
申请号：US15953805
申请日：2018-04-16
发明人： James A. O'Connor, JR. , Barry M. Trager , Warren E. Maule , Marc A. Gollub , Brad W. Michael , Patrick J. Meaney
摘要： Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
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公开(公告)号：US10353669B2
公开(公告)日：2019-07-16
申请号：US15255543
申请日：2016-09-02
摘要： Managing entries in a mark table of computer memory errors including identifying at least two mark table entries as candidates for merger, wherein each mark table entry indicates an error at a location in a computer memory; and merging the identified mark table entries into a single mark table entry, including removing one of the identified mark table entries from the mark table.
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