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公开(公告)号：US10296417B2
公开(公告)日：2019-05-21
申请号：US16043362
申请日：2018-07-24
发明人： Glenn D. Gilda , Patrick J. Meaney
摘要： In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.
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公开(公告)号：US20160371159A1
公开(公告)日：2016-12-22
申请号：US15262111
申请日：2016-09-12
发明人： Patrick J. Meaney , Glenn D. Gilda , Eric E. Retter , John S. Dodson , Gary A. Van Huben , Brad W. Michael , Stephen J. Powell
IPC分类号： G06F11/16 , G11C11/4093 , G11C11/4076
CPC分类号： G06F11/1679 , G06F1/04 , G06F1/10 , G06F1/12 , G06F1/32 , G06F11/1497 , G06F11/1604 , G06F11/1675 , G06F13/1689 , G06F13/1694 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/4076 , G11C11/4093 , G11C29/52
摘要： Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.
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公开(公告)号：US20150318058A1
公开(公告)日：2015-11-05
申请号：US14266984
申请日：2014-05-01
CPC分类号： G06F12/02 , G06F11/106 , G06F11/26 , G06F11/261 , G06F11/263 , G06F12/0253 , G06F2212/1032 , G06F2212/1044 , G11C11/41 , G11C29/02 , G11C29/10 , G11C29/44 , G11C2029/0409
摘要： Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.
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公开(公告)号：US20140281653A1
公开(公告)日：2014-09-18
申请号：US13835258
申请日：2013-03-15
IPC分类号： G06F1/12
CPC分类号： G06F11/1662 , G06F1/04 , G06F1/10 , G06F1/12 , G06F3/0614 , G06F3/0619 , G06F3/0629 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G06F11/0757 , G06F11/1044 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F13/1673
摘要： Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.
摘要翻译： 实施例涉及重新建立在存储器系统中的多个通道之间的同步。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括接收与至少一个信道相关联的失步指示的方法。 存储器控制单元执行重新建立同步的第一阶段，其包括选择性地停止多个信道上的新业务，等待第一时间段到期，基于第一时间段到期，恢复多个信道上的业务，并验证 同步在第二时间段重新建立。
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公开(公告)号：US10055287B2
公开(公告)日：2018-08-21
申请号：US15810722
申请日：2017-11-13
发明人： Glenn D. Gilda , Patrick J. Meaney
CPC分类号： G06F11/1068 , G06F11/1048 , G06F11/106 , G11C29/44 , G11C29/52
摘要： In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.
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公开(公告)号：US20180060167A1
公开(公告)日：2018-03-01
申请号：US15810722
申请日：2017-11-13
发明人： Glenn D. Gilda , Patrick J. Meaney
CPC分类号： G06F11/1068 , G06F11/1048 , G06F11/106 , G11C29/44 , G11C29/52
摘要： In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.
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公开(公告)号：US20170091023A1
公开(公告)日：2017-03-30
申请号：US14870347
申请日：2015-09-30
发明人： Glenn D. Gilda , Patrick J. Meaney
CPC分类号： G06F11/1068 , G06F11/1048 , G06F11/106 , G11C29/44 , G11C29/52
摘要： In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.
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公开(公告)号：US09535778B2
公开(公告)日：2017-01-03
申请号：US13835258
申请日：2013-03-15
CPC分类号： G06F11/1662 , G06F1/04 , G06F1/10 , G06F1/12 , G06F3/0614 , G06F3/0619 , G06F3/0629 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G06F11/0757 , G06F11/1044 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F13/1673
摘要： Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.
摘要翻译： 实施例涉及重新建立在存储器系统中的多个通道之间的同步。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括接收与至少一个信道相关联的失步指示的方法。 存储器控制单元执行重新建立同步的第一阶段，其包括选择性地停止多个信道上的新业务，等待第一时间段到期，基于第一时间段到期，恢复多个信道上的业务，并验证 同步在第二时间段重新建立。
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公开(公告)号：US09495231B2
公开(公告)日：2016-11-15
申请号：US15072659
申请日：2016-03-17
CPC分类号： G06F11/1662 , G06F1/04 , G06F1/10 , G06F1/12 , G06F3/0614 , G06F3/0619 , G06F3/0629 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G06F11/0757 , G06F11/1044 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F13/1673
摘要： Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving an out-of-synchronization indication associated with at least one of the channels. The memory control unit performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.
摘要翻译： 实施例涉及重新建立在存储器系统中的多个通道之间的同步。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括接收与至少一个信道相关联的失步指示的方法。 存储器控制单元执行重新建立同步的第一阶段，其包括选择性地停止多个信道上的新业务，等待第一时间段到期，基于第一时间段到期，恢复多个信道上的业务，并验证 同步在第二时间段重新建立。
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公开(公告)号：US09037811B2
公开(公告)日：2015-05-19
申请号：US13835282
申请日：2013-03-15
CPC分类号： G06F13/16 , G06F3/0656 , G06F3/0659 , G06F13/1642 , G06F13/1689
摘要： Embodiments relate to tagging in a MCU. An aspect includes assigning a command tag to a command by a tag allocation logic of the MCU. Another aspect includes sending the command and the command tag on a plurality of channels that are in communication with the MCU. Another aspect includes receiving a response tag comprising one of a data tag and a done tag corresponding to the command tag from each of the plurality of channels. Another aspect includes, based on receiving a data tag from each of the plurality of channels, determining that read data corresponding to the command is available.
摘要翻译： 实施例涉及MCU中的标签。 一个方面包括通过MCU的标签分配逻辑将命令标签分配给命令。 另一方面包括在与MCU通信的多个信道上发送命令和命令标签。 另一方面包括从多个频道中的每一个接收包括与命令标签对应的数据标签和完成标签之一的响应标签。 另一方面包括：基于从多个通道中的每一个接收数据标签，确定对应于该命令的读取数据是可用的。
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