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506 条记录 (耗时 0.028 秒)

    Field Effect Transistor Device with Raised Active Regions
    111.
    发明申请
    Field Effect Transistor Device with Raised Active Regions 失效
    具有有源区域的场效应晶体管器件

    公开(公告)号：US20130071979A1

    公开(公告)日：2013-03-21

    申请号：US13606382

    申请日：2012-09-07

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L21/336

    CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

    摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.

    摘要翻译： 一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分 具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面， 第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。

    Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same
    114.
    发明申请
    Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same 有权
    极薄的绝缘体上半导体（ETSOI）FET，具有阶梯式引出源/漏极及其形成方法

    公开(公告)号：US20120061759A1

    公开(公告)日：2012-03-15

    申请号：US12882490

    申请日：2010-09-15

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam Shahidi

    IPC分类号： H01L29/786 ,  H01L21/782

    CPC分类号： H01L29/78654 ,  H01L29/66628 ,  H01L29/66772

    摘要： A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.

    摘要翻译： 在具有厚度范围为3nm至20nm的半导体层的绝缘体上半导体（SOI）衬底的顶部上形成MOSFET器件。 在SOI衬底的顶部上形成阶梯形凸起的延伸部，凸起的源极区域和凸起的漏极区域（S / D）。 更薄的凸起的延伸区域邻近薄的栅极侧壁间隔物，降低延伸电阻而不显着增加寄生电阻。 单个外延生长优选同时形成更薄的凸起延伸和较高的凸起S / D，从而降低制造成本以及升高的S / D与延伸部之间的接触电阻。 还提供了形成上述MOSFET器件的方法。

    TUNNEL FIELD EFFECT TRANSISTOR
    115.
    发明申请
    TUNNEL FIELD EFFECT TRANSISTOR 有权
    隧道场效应晶体管

    公开(公告)号：US20110254080A1

    公开(公告)日：2011-10-20

    申请号：US12760287

    申请日：2010-04-14

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

    摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.

    摘要翻译： 公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。 该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。 形成覆盖栅极堆叠和结的硬掩模。 执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。 去除硬掩模的注入部分，并露出其中一个接头。 该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。 还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

    High-performance FETs with embedded stressors
    117.
    发明授权
    High-performance FETs with embedded stressors 有权
    具有嵌入式应力的高性能FET

    公开(公告)号：US08022488B2

    公开(公告)日：2011-09-20

    申请号：US12566004

    申请日：2009-09-24

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L21/02

    CPC分类号： H01L29/7848 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

    摘要翻译： 提供了高性能半导体结构和制造这种结构的方法。 半导体结构包括位于半导体衬底的上表面上的至少一个栅堆叠，例如FET。 该结构还包括在至少一个栅极堆叠的沟道上引起应变的第一外延半导体材料。 第一外延半导体材料位于至少一个栅极堆叠的基准面上，基本上位于衬底中的存在于至少一个栅极堆叠的相对侧上的一对凹陷区域内。 扩散扩展区域位于每个凹陷区域中的所述第一外延半导体材料的上表面内。 该结构还包括位于扩散扩展区的上表面上的第二外延半导体材料。 第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

    High-K/metal gate CMOS finFET with improved pFET threshold voltage
    118.
    发明授权
    High-K/metal gate CMOS finFET with improved pFET threshold voltage 有权
    高K /金属栅极CMOS finFET，具有改善的pFET阈值电压

    公开(公告)号：US07993999B2

    公开(公告)日：2011-08-09

    申请号：US12614906

    申请日：2009-11-09

    申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

    发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

    摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

    摘要翻译： 用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。 施主材料外延地沉积在鳍结构的暴露的侧壁上。 施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。 施主材料被去除，并且从翅片结构形成场效应晶体管。

    Semiconductor device with epitaxial source/drain facetting provided at the gate edge
    119.
    发明授权
    Semiconductor device with epitaxial source/drain facetting provided at the gate edge 有权
    具有外延源/漏极平面的半导体器件设置在栅极边缘

    公开(公告)号：US08916443B2

    公开(公告)日：2014-12-23

    申请号：US13534407

    申请日：2012-06-27

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L21/8238 ,  H01L27/12 ,  G06F17/50

    CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/0653

    摘要： A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.

    摘要翻译： 形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。 栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。 凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域 涉及对应于第二晶体管的第一晶体管和第二升高区域。 第一凸起区域和第二凸起区域由至少一个沟槽电隔离。