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    THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHS
    111.
    发明申请
    THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHS 有权
    具有不同器件宽度的三维FET器件

    公开(公告)号：US20130015534A1

    公开(公告)日：2013-01-17

    申请号：US13184537

    申请日：2011-07-16

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7854

    摘要： A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure.

    摘要翻译： 一种三维FET器件结构，其包括多个三维FET器件。 三维FET器件中的每一个包括绝缘基底，垂直于绝缘基底取向的三维鳍片，围绕三维翅片缠绕的栅极电介质和围绕栅极电介质缠绕并垂直于三维翅片延伸的栅极， 具有将器件宽度定义为与栅极电介质接触的三维鳍片的圆周的三维鳍片。 三维FET器件中的至少一个具有第一器件宽度，而三维FET器件中的至少一个具有第二器件宽度。 第一个设备宽度与第二个设备宽度不同。 还包括制造三维FET器件结构的方法。

    Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same
    112.
    发明授权
    Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same 有权
    具有片上电阻的非常薄的绝缘体上半导体（ETSOI）集成电路及其形成方法

    公开(公告)号：US08343819B2

    公开(公告)日：2013-01-01

    申请号：US12687273

    申请日：2010-01-14

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1214 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/13

    摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.

    摘要翻译： 提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。 在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。 由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。 还提供了形成上述电气装置的方法。

    Raised Source/Drain Field Effect Transistor
    113.
    发明申请
    Raised Source/Drain Field Effect Transistor 审中-公开
    提升源极/漏极场效应晶体管

    公开(公告)号：US20120329232A1

    公开(公告)日：2012-12-27

    申请号：US13602644

    申请日：2012-09-04

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/84 ,  H01L29/66628

    摘要： In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.

    摘要翻译： 在本发明的一个示例性实施例中，半导体结构包括：衬底; 以及至少部分地覆盖所述衬底的多个器件，其中所述多个器件包括经由具有第一长度的第一升高源极/漏极耦合到第二器件的第一器件，其中所述第一器件进一步耦合到第二升高源 /漏极，其中第一器件包括晶体管，其中第一升高源极/漏极和第二升高源极/漏极至少部分地超过衬底，其中第二升高源极/漏极包括端子电接触，其中 第二长度大于第一长度。

    SOI Trench Dram Structure With Backside Strap
    114.
    发明申请
    SOI Trench Dram Structure With Backside Strap 有权
    具有背面表带的SOI沟槽结构

    公开(公告)号：US20120299075A1

    公开(公告)日：2012-11-29

    申请号：US13568601

    申请日：2012-08-07

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

    摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.

    摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背面带的至少第一部分位于掺杂部分的下面，背侧带在背面带的第一端和电容器处耦合到顶部硅层的掺杂部分 在背面带的第二端; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

    Tunnel field effect transistor
    115.
    发明授权
    Tunnel field effect transistor 有权
    隧道场效应晶体管

    公开(公告)号：US08318568B2

    公开(公告)日：2012-11-27

    申请号：US12760287

    申请日：2010-04-14

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

    摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.

    摘要翻译： 公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。 该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。 形成覆盖栅极堆叠和结的硬掩模。 执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。 去除硬掩模的注入部分，并露出其中一个接头。 该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。 还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

    Extremely Thin Semiconductor-On-Insulator (ETSOI) FET With A Back Gate and Reduced Parasitic Capacitance And Method of Forming The Same
    116.
    发明申请
    Extremely Thin Semiconductor-On-Insulator (ETSOI) FET With A Back Gate and Reduced Parasitic Capacitance And Method of Forming The Same 有权
    具有背栅极和减少寄生电容的极薄半导体绝缘体（ETSOI）FET及其形成方法

    公开(公告)号：US20120292700A1

    公开(公告)日：2012-11-22

    申请号：US13108282

    申请日：2011-05-16

    申请人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris

    发明人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/764 ,  H01L21/84 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78648 ,  H01L2029/42388

    摘要： An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric.

    摘要翻译： 在SOI衬底上的非常薄的SOI MOSFET器件在Si衬底上设置有由薄BOX层叠加的背栅层; 在薄BOX层顶部的非常薄的SOI层（ETSOI）; 并且在ETSOI层上的FET器件具有由间隔物绝缘的栅极堆叠。 薄的BOX形成在ETSOI通道下面，并在源极和漏极之间提供较厚的电介质，以减少源极/漏极到背栅极寄生电容。 较厚的电介质部分与栅极自对准。 较厚电介质部分内的空隙形成在源/漏区下。 背栅由通过注入损坏的半导体区域确定，并且通过横向蚀刻形成绝缘层并且用电介质反向填充。

    Strained thin body CMOS with Si:C and SiGe stressor
    118.
    发明申请
    Strained thin body CMOS with Si:C and SiGe stressor 审中-公开
    应变薄体CMOS与Si：C和SiGe应力

    公开(公告)号：US20120276695A1

    公开(公告)日：2012-11-01

    申请号：US13098352

    申请日：2011-04-29

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845

    摘要： A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement.

    摘要翻译： 公开了一种方法，其特征在于用于超薄平面和FinFET CMOS器件的凸起源极/漏极和应变体的处理集成。 NFET和PFET器件通过用于PFET器件的原位p型掺杂SiGe的选择性外延以及用于NFET器件的原位n型掺杂Si：C来提高其源极/漏极。 这种升高的源极/漏极提供低的寄生电阻，并且它们对于相应的载流子，电子或空穴，迁移率增强赋予了正确符号的器件体上的应变。