公开(公告)号：US08116134B2

公开(公告)日：2012-02-14

申请号：US12342297

申请日：2008-12-23

申请人： Noboru Shibata ,  Kazunori Kanebako

发明人： Noboru Shibata ,  Kazunori Kanebako

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C29/00 ,  G11C2211/5621

摘要： Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h≦n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells.

摘要翻译： 存储单元将k位数据（k是不小于2的自然数）存储到单个单元中。 数字n个数据存储电路存储外部提供的k位数据以将数据写入存储单元。 控制电路输入第一页，第二页上的数据。 。 。 ，第k页到数据存储电路的每个h（h＆nlE; n），然后将数据写入n个数据存储电路到存储单元中。

公开(公告)号：US20110205805A1

公开(公告)日：2011-08-25

申请号：US12672335

申请日：2008-09-02

申请人： Mitsuaki Honma ,  Noboru Shibata

发明人： Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5646

摘要： A semiconductor memory device executes a writing operation based on a first bit assignment pattern at the time of writing. The first bit assignment pattern is created such that pieces of x-bit data assigned to adjacent threshold distributions have only a one-bit difference therebetween and an alignment of data on the same digit of 2x pieces of x-bit data corresponding to an alignment of 2x pieces of threshold distributions contains at least two transition points of “0” and “1”. The semiconductor memory device operates at the time of reading such that a read voltage corresponding to the transition points of “0” and “1” is applied to the word line on a page basis to determine x-bit data stored in the memory cell one-bit by one-bit based on the first assignment pattern. The page contains a set of data on the same digit bit in pieces of x-bit data stored in the memory cells connected to the word line.

摘要翻译： 半导体存储器件在写入时基于第一位分配模式执行写入操作。 第一位分配模式被创建，使得分配给相邻阈值分布的X位数据片段之间只有一位差异，并且对应于与x位数据对齐的2个x位数据的相同数位上的数据对齐 2个阈值分布包含至少两个转换点“0”和“1”。 半导体存储器件在读取时操作，使得对应于“0”和“1”的转换点的读取电压在页面上施加到字线，以确定存储在存储器单元中的x位数据 - 基于第一个分配模式位1比特。 该页面包含存储在连接到字线的存储单元中的x位数据的相同位数位上的一组数据。

公开(公告)号：US08004889B2

公开(公告)日：2011-08-23

申请号：US12407295

申请日：2009-03-19

申请人： Noboru Shibata

发明人： Noboru Shibata

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10

摘要： A memory cell array is configured so that a plurality of memory cells storing one value of an n value (n is a natural number more than 2) are arranged in a matrix. A control circuit controls the voltage of a word line and a bit line in accordance with input data. The control circuit supplies a first voltage to a word line of a selected cell in a write operation, and supplies a second voltage to at least one word line adjacent to the selected cell. Thereafter, the control circuit changes a voltage of the at least one word line adjacent to the selected cell from the second voltage to a third voltage (second voltage

摘要翻译： 存储单元阵列被配置为使得存储n值（n是大于2的自然数）的一个值的多个存储单元被布置成矩阵。 控制电路根据输入数据控制字线和位线的电压。 控制电路在写操作中将第一电压提供给所选单元的字线，并将第二电压提供给与所选单元相邻的至少一个字线。 此后，控制电路将与所选择的单元相邻的至少一个字线的电压从第二电压改变为第三电压（第二电压<第三电压），并且还改变所选单元的字线的电压 从第一电压到第四电压（第一电压<第四电压）。

公开(公告)号：US07978514B2

公开(公告)日：2011-07-12

申请号：US12837595

申请日：2010-07-16

申请人： Noboru Shibata ,  Tomoharu Tanaka

发明人： Noboru Shibata ,  Tomoharu Tanaka

IPC分类号： G11C11/34

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5646 ,  G11C2211/5648 ,  G11C2216/14

摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.

摘要翻译： 数据存储电路以一一对应的方式连接到位线。 写电路将第一页上的数据写入由字线同时选择的多个第一存储单元。 此后，写电路将第二页上的数据写入多个第一存储单元。 然后，写入电路将第一和第二页面上的数据写入与位线方向相邻的第一存储单元的第二存储单元。

公开(公告)号：US20110141811A1

公开(公告)日：2011-06-16

申请号：US13033309

申请日：2011-02-23

申请人： Takahiro Shimizu ,  Noboru Shibata

发明人： Takahiro Shimizu ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641 ,  G11C2211/5643

摘要： A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.

摘要翻译： 本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括具有多个存储单元的第一区域，每个存储器单元能够存储n位数据（n为自然数）和具有多个存储单元的第二区域 每个能够存储k比特数据（k> n：k是自然数），包括多个数据高速缓存的数据存储电路，以及控制该存储单元阵列和数据存储电路的控制电路 将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式，并将k位数据存储到第二区域中的存储单元中。

公开(公告)号：US20110096605A1

公开(公告)日：2011-04-28

申请号：US12985427

申请日：2011-01-06

申请人： Yasukazu Kosaki ,  Noboru Shibata

发明人： Yasukazu Kosaki ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

摘要翻译： 一种其中布置有NAND单元单元的半导体存储器件，所述NAND单元单元包括：串联连接的多个电可重写和非易失性存储单元; 设置在NAND单元单元的两端的第一和第二选择栅晶体管分别用于将其耦合到位线和源极线; 以及在NAND单元单元中与第一和第二选择栅极晶体管相邻设置的虚设单元，其中虚设单元被设置为具有比存储单元的擦除状态的阈值电压高的阈值电压的状态。

公开(公告)号：US07916534B2

公开(公告)日：2011-03-29

申请号：US11737373

申请日：2007-04-19

申请人： Takahiro Shimizu ,  Noboru Shibata

发明人： Takahiro Shimizu ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641 ,  G11C2211/5643

摘要： A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.

摘要翻译： 本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括具有多个存储单元的第一区域，每个存储器单元能够存储n位数据（n为自然数）和具有多个存储单元的第二区域 每个能够存储k比特数据（k> n：k是自然数），包括多个数据高速缓存的数据存储电路，以及控制该存储单元阵列和数据存储电路的控制电路 将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式，并将k位数据存储到第二区域中的存储单元中。

公开(公告)号：US07869280B2

公开(公告)日：2011-01-11

申请号：US11862539

申请日：2007-09-27

申请人： Yasukazu Kosaki ,  Noboru Shibata

发明人： Yasukazu Kosaki ,  Noboru Shibata

IPC分类号： G11C16/10

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

摘要翻译： 一种其中布置有NAND单元单元的半导体存储器件，所述NAND单元单元包括：串联连接的多个电可重写和非易失性存储单元; 设置在NAND单元单元的两端的第一和第二选择栅晶体管分别用于将其耦合到位线和源极线; 以及在NAND单元单元中与第一和第二选择栅极晶体管相邻设置的虚设单元，其中虚设单元被设置为具有比存储单元的擦除状态的阈值电压高的阈值电压的状态。

公开(公告)号：US07864592B2

公开(公告)日：2011-01-04

申请号：US12551936

申请日：2009-09-01

申请人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

发明人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/1051 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5649 ,  G11C2211/565 ,  G11C2216/14

摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

公开(公告)号：US07843723B2

公开(公告)日：2010-11-30

申请号：US11780656

申请日：2007-07-20

申请人： Noboru Shibata

发明人： Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/26

摘要： A control unit reads data from a plurality of memory cells connected to one of the word lines in a read operation at a first level CR generated by a voltage generator circuit and in a read operation at a second level CR−x and finds the number of cells included between the first level and the second level from the data and, if the number is equal to or smaller than a specified value, determines the result of the read operation at the first level to be read data.

摘要翻译： 在由电压发生器电路产生的第一电平CR和在第二电平CR-x的读取操作中的读取操作中，控制单元从连接到一个字线的多个存储器单元中读取数据， 从数据中包含在第一级和第二级之间的单元，并且如果该数量等于或小于指定值，则将在第一级的读操作的结果确定为读数据。