公开(公告)号：US06521938B2

公开(公告)日：2003-02-18

申请号：US09203383

申请日：1998-12-02

申请人： Takeshi Hamamoto

发明人： Takeshi Hamamoto

IPC分类号： H01L27108

CPC分类号： H01L27/10861 ,  H01L27/10867 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/945

摘要： MOS transistors are formed on island-shaped divided element regions of a silicon substrate, and provided with gate electrodes having the same widths as the element regions. Thereafter, capacitor grooves are formed at end portions of the element regions, and capacitor insulating films formed of BSTO are provided on inner walls of the capacitor grooves. Then, the capacitor grooves are filled with storage electrodes, thereby forming capacitors. Furthermore, connection conductors are formed to connect the storage electrodes and source diffusion layers of the MOS transistors. Then, word lines are formed to connect the gate electrodes of the MOS transistors, and further bit lines are formed to connect drain diffusion layers of the MOS transistors.

摘要翻译： MOS晶体管形成在硅衬底的岛状分割元件区上，并且设置有与元件区域相同宽度的栅电极。 其后，在元件区域的端部形成电容器槽，在电容器槽的内壁上设置由BSTO形成的电容绝缘膜。 然后，电容器槽填充有存储电极，从而形成电容器。 此外，形成连接导体以连接MOS晶体管的存储电极和源极扩散层。 然后，形成字线以连接MOS晶体管的栅电极，并且形成另外的位线以连接MOS晶体管的漏极扩散层。

公开(公告)号：US06449198B1

公开(公告)日：2002-09-10

申请号：US09717375

申请日：2000-11-22

申请人： Kei Hamade ,  Takeshi Hamamoto ,  Masaru Haraguchi ,  Yasuhiro Konishi

发明人： Kei Hamade ,  Takeshi Hamamoto ,  Masaru Haraguchi ,  Yasuhiro Konishi

IPC分类号： G11C700

CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C11/4097

摘要： In the SDRAM, a selector selects one of four global IO line pairs according to a column block select signal and a word configuration selecting signal, and connects the selected global IO line pair to an input/output node pair of a preamplifier in a pulsed manner for a prescribed period of time. Since the equalization of the global IO line pair can be started immediately after the global IO line pair is connected in a pulsed manner to the input/output node pair of the preamplifier, longer equalization period for the global IO line can be set aside so that the read operation can be stabilized.

摘要翻译： 在SDRAM中，选择器根据列块选择信号和字配置选择信号来选择四个全局IO线对中的一个，并将所选择的全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对 在规定的时间内。 由于全局IO线对的均衡可以在全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对之后立即开始，所以可以将全局IO线的更长的均衡周期放在一边，以便 读取操作可以稳定。

公开(公告)号：US06335887B1

公开(公告)日：2002-01-01

申请号：US09727544

申请日：2000-12-04

申请人： Shigekazu Aoki ,  Seiji Sawada ,  Mikio Asakura ,  Takeshi Hamamoto ,  Masakazu Hirose

发明人： Shigekazu Aoki ,  Seiji Sawada ,  Mikio Asakura ,  Takeshi Hamamoto ,  Masakazu Hirose

IPC分类号： G11C700

CPC分类号： G11C29/34

摘要： The semiconductor memory device has a word configuration determination signal generating circuit including a plurality of generating circuits, each of which is formed of two clocked inverters and two inverters. In a normal operation mode, a test mode signal TX4 is inactivated and a word configuration determination signal [x16E] of an H level is output. In a test mode, the test mode signal TX4 is activated and a word configuration determination signal [x4E] of an H level is output. Thus, in the test mode, the word configuration is switched to the one that is smaller than in the normal operation mode. This allows simultaneous testing of a larger number of semiconductor memory devices.

公开(公告)号：US06333895B1

公开(公告)日：2001-12-25

申请号：US09678792

申请日：2000-10-04

申请人： Takeshi Hamamoto ,  Satoshi Kawasaki

发明人： Takeshi Hamamoto ,  Satoshi Kawasaki

IPC分类号： G11C800

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4074

摘要： In an output data control circuit for transferring complementary data signals read from a memory array to an external data output node in accordance with an output clock signal, a clocked gate circuit transferring complementary data signals in synchronization with an output clock signal and an output data latch circuit latching an output signal of the clocked gate circuit are operated using a voltage level not exceeding an internal power supply voltage, and the complementary data signals read from a memory cell is subjected to an amplitude expanding processing in a stage preceding the clocked gate circuit, and then is applied to the clocked gate circuit. A clock synchronous semiconductor memory device allowing reduction of a clock access time is provided.

摘要翻译： 在根据输出时钟信号将从存储器阵列读取的互补数据信号传送到外部数据输出节点的输出数据控制电路中，与输出时钟信号和输出数据锁存器同步地传送互补数据信号的时钟门电路 使用不超过内部电源电压的电压电平来操作锁定时钟门电路的输出信号的电路，并且从存储器单元读取的互补数据信号在时钟门电路之前的阶段中进行幅度扩展处理， 然后施加到时钟门电路。 提供了一种允许减少时钟访问时间的时钟同步半导体存储器件。

公开(公告)号：US06317368B1

公开(公告)日：2001-11-13

申请号：US09669658

申请日：2000-09-26

申请人： Yasuhiko Taito ,  Takeshi Hamamoto ,  Tetsuo Kato

发明人： Yasuhiko Taito ,  Takeshi Hamamoto ,  Tetsuo Kato

IPC分类号： G11C700

CPC分类号： G11C16/3468

摘要： Data are read out from sub-arrays within a memory cell array in batches. A data bus driving circuit compares the read data, and, according to the comparison result, drives the potentials of data buses with small amplitudes. A data retaining circuit retains fail information indicating the presence of a fail bit, according to the data on the data buses. The data retaining circuit responds to an externally supplied designation, and provides a pass/fail information output circuit with the fail information with large amplitude. The fail information is further output to the outside.

摘要翻译： 批量从存储单元阵列中的子阵列中读出数据。 数据总线驱动电路将读取的数据进行比较，并且根据比较结果，驱动具有小振幅的数据总线的电位。 根据数据总线上的数据，数据保持电路保留指示故障位的存在的失败信息。 数据保持电路响应外部提供的指定，并提供具有大振幅的失败信息的通过/失败信息输出电路。 故障信息进一步输出到外部。

公开(公告)号：US6087691A

公开(公告)日：2000-07-11

申请号：US853180

申请日：1997-05-07

申请人： Takeshi Hamamoto

发明人： Takeshi Hamamoto

IPC分类号： H01L27/11 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L27/0251 ,  H01L27/108

摘要： On a p.sup.++ substrate (1) provided is a p.sup.- epitaxial layer (2) having an impurity concentration lower than that of the p.sup.++ substrate (1). A p well (3) is formed in a portion of the p.sup.- epitaxial layer 2 and further n.sup.+ diffusion layers (4a and 4b) are selectively formed in the p well (3). A memory cell capacitor (5) is connected onto the n.sup.+ diffusion layer 4b. On the other hand, an no diffusion layer (6) is selectively formed in the p.sup.- epitaxial layer (2) separately from the p well (3), to which an external signal input circuit (7) is connected. Further, a p.sup.++ diffusion layer 9a is provided between the external signal input circuit (7) serving as a source for injection of the minority carriers, i.e., electrons and the n.sup.+ diffusion layer (4b) connected to the memory cell capacitor (5), for blocking the entry of the minority carries. The p.sup.++ diffusion layer (9a) extends up to such a depth as to reach the p.sup.++ substrate (1) from a surface of the p.sup.- epitaxial layer (2). Having this structure, a semiconductor device which does not allow the electrons injected to the p.sup.- epitaxial layer from the external signal input circuit to reach the memory cell capacitor can be provided.

摘要翻译： 在p ++衬底（1）上提供的杂质浓度低于p ++衬底（1）的p-外延层（2）。 p阱（3）形成在p外延层2的一部分中，并且在p阱（3）中选择性地形成另外的n +扩散层（4a和4b）。 存储单元电容器（5）连接到n +扩散层4b上。 另一方面，与p阱（3）分开地在p-外延层（2）中选择性地形成无扩散层（6），外部信号输入电路（7）连接到该p外延层。 此外，在用作少数载流子注入源的外部信号输入电路（7）之间设置p ++扩散层9a，即与存储单元电容器（5）连接的电子和n +扩散层（4b） 阻止少数人进入。 p ++扩散层（9a）延伸到从p-外延层（2）的表面到达p ++衬底（1）的深度。 具有这种结构，可以提供不允许从外部信号输入电路注入到p外延层的电子到达存储单元电容器的半导体器件。

公开(公告)号：US5936459A

公开(公告)日：1999-08-10

申请号：US942485

申请日：1997-10-02

申请人： Takeshi Hamamoto

发明人： Takeshi Hamamoto

IPC分类号： G11C11/407 ,  G11C11/409 ,  H01L21/8238 ,  H01L27/092 ,  H02M3/07 ,  H03K3/01

CPC分类号： H02M3/07

摘要： A first charge pumping circuit including a first capacitor and first and second switches, and a second charge pumping circuit including a second capacitor and third and fourth switches, are operated complementarily. The first capacitor is provided between first and second nodes, and the second capacitor is provided between third and fourth nodes. An NMOS transistor as equalizing means is provided between the first and third nodes. Before the start of supply of charges by the second switch to the second node and injection of charges by the third switch to an output node, the NMOS transistor is turned on, whereby potentials at the first and third nodes are equalized. Accordingly, the charges consumed by the first charge pumping circuit can be recycled by the second charge pumping circuit. Thus, lower power consumption is realized.

摘要翻译： 包括第一电容器和第一和第二开关的第一电荷泵浦电路和包括第二电容器和第三和第四开关的第二电荷泵浦电路互补地操作。 第一电容器设置在第一和第二节点之间，第二电容器设置在第三和第四节点之间。 在第一和第三节点之间提供作为均衡装置的NMOS晶体管。 在开始通过第二开关向第二节点提供电荷并且通过第三开关向输出节点注入电荷之前，NMOS晶体管导通，由此第一和第三节点处的电位相等。 因此，第一电荷泵送电路消耗的电荷可以由第二电荷泵送电路再循环。 因此，实现了较低的功耗。

公开(公告)号：US5508541A

公开(公告)日：1996-04-16

申请号：US124300

申请日：1993-09-20

申请人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

发明人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10829

摘要： A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.

摘要翻译： MOS随机存取存储器件包括其中形成有沟槽的半导体衬底和衬底上的存储器单元的阵列。 每个存储单元包括1位数据存储电容器和转移栅极MOS晶体管。 电容器包括埋在沟槽中的绝缘层，其用作存储节点。 岛状半导体层至少部分地覆盖基板上的存储节点层，并且与其耦合。 晶体管具有源极和漏极，在衬底中限定其间的沟道区域，以及覆盖沟道区域的绝缘栅极。 源极和漏极中的一个直接耦合到岛状层，而另一个与与其相关联的相应数据传输线（位线）接触。

公开(公告)号：US5481496A

公开(公告)日：1996-01-02

申请号：US236004

申请日：1994-05-02

申请人： Toshifumi Kobayashi ,  Yoshikazu Morooka ,  Michihiro Yamada ,  Takeshi Hamamoto

发明人： Toshifumi Kobayashi ,  Yoshikazu Morooka ,  Michihiro Yamada ,  Takeshi Hamamoto

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/065 ,  G11C7/1006 ,  G11C7/12

摘要： Sense amplifiers provided for each of the bit line pairs are divided into groups to be independently driven, whereby the influence of sense amplifiers of different groups can be prevented, and therefore the destruction of data of the non-selected memory cells during data transfer can be prevented. In transferring data from the data register to the memory cell array, the sense amplifier is not activated until the stored information of the memory cells selected by the word line is fully read to the corresponding bit lines, whereby the destruction of data stored in the non-selected memory cells can be prevented.

摘要翻译： 为每个位线对提供的感测放大器被分成要被独立驱动的组，由此可以防止不同组的读出放大器的影响，因此数据传送期间未选择的存储器单元的数据的破坏可以是 防止了 在将数据从数据寄存器传送到存储单元阵列时，读出放大器不会被激活，直到由字线选择的存储单元的存储信息被完全读出到相应的位线为止， 可以防止选择的存储单元。

公开(公告)号：US5130945A

公开(公告)日：1992-07-14

申请号：US551268

申请日：1990-07-12

申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Masaaki Mihara

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04 ,  G11C15/043

摘要： Each match line is connected to a plurality of CAM cells constituting a CAM array. The respective CAM cells store data applied through a bit line and an inverted-bit line in its data storage portion when selected by a word line. The stored data are applied to a data comparison portion to be compared with retrieval data applied through the bit line and the inverted-bit line, thereby detecting match or mismatch therebetween. A comparison result of the data comparison portion is first stored in a capacitance element in the form of charge. In order to prevent escape of the information stored in the capacitance element, a blocking means blocks a part of a charge and discharge path for the capacitance element. A charge transfer means provided between the capacitance element and the match line transfers a certain amount of charge from either one to the other when information of mismatch is stored in the capacitance element. This causes fluctuation of charge potential on the match line. The fluctuation of potential on the match line depends on the number of mismatched CAM cells out of a plurality of CAM cells connected to the match line. Therefore, detection of potential on the match line permits detecting the number of mismatched CAM cells.

摘要翻译： 每个匹配线连接到构成CAM阵列的多个CAM单元。 当通过字线选择时，相应的CAM单元存储在其数据存储部分中通过位线和反相位线施加的数据。 将存储的数据应用于数据比较部分，以与通过位线和反向位线施加的检索数据进行比较，从而检测它们之间的匹配或失配。 数据比较部分的比较结果首先以电荷的形式存储在电容元件中。 为了防止存储在电容元件中的信息的逸出，阻塞装置阻挡电容元件的充电和放电路径的一部分。 当在电容元件中存储不匹配的信息时，设置在电容元件和匹配线之间的电荷转移装置将一定量的电荷从两者之一传递到另一个。 这导致匹配线上的电荷电位波动。 匹配线上的电位波动取决于连接到匹配线的多个CAM单元中不匹配的CAM单元的数量。 因此，匹配线上的电位检测允许检测不匹配的CAM单元的数量。