公开(公告)号：US5146300A

公开(公告)日：1992-09-08

申请号：US830971

申请日：1992-02-10

申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

IPC分类号： G11C15/04 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C15/043

摘要： A semiconductor integrated circuit device including a semiconductor substrate having a main surface; a first conductive region formed on the main surface; a second conductive region formed on the main surface, spaced apart from the first conductive region and to be electrically connected to the first conductive region; and a capacitor having a storage node connecting the first and second conductive regions. The storage node serves to connect the first and second conductive regions and simultaneously stores charges. In other aspects of the invention, there are provided a memory cell having a structure described above, and a method of manufacturing the above-described semiconductor integrated circuit device.

摘要翻译： 一种半导体集成电路器件，包括：具有主表面的半导体衬底; 形成在所述主表面上的第一导电区域; 形成在所述主表面上的第二导电区域，与所述第一导电区域间隔开并且电连接到所述第一导电区域; 以及具有连接第一和第二导电区域的存储节点的电容器。 存储节点用于连接第一和第二导电区域并同时存储电荷。 在本发明的其他方面，提供了一种具有上述结构的存储单元，以及制造上述半导体集成电路器件的方法。

公开(公告)号：US5130945A

公开(公告)日：1992-07-14

申请号：US551268

申请日：1990-07-12

申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Masaaki Mihara

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04 ,  G11C15/043

摘要： Each match line is connected to a plurality of CAM cells constituting a CAM array. The respective CAM cells store data applied through a bit line and an inverted-bit line in its data storage portion when selected by a word line. The stored data are applied to a data comparison portion to be compared with retrieval data applied through the bit line and the inverted-bit line, thereby detecting match or mismatch therebetween. A comparison result of the data comparison portion is first stored in a capacitance element in the form of charge. In order to prevent escape of the information stored in the capacitance element, a blocking means blocks a part of a charge and discharge path for the capacitance element. A charge transfer means provided between the capacitance element and the match line transfers a certain amount of charge from either one to the other when information of mismatch is stored in the capacitance element. This causes fluctuation of charge potential on the match line. The fluctuation of potential on the match line depends on the number of mismatched CAM cells out of a plurality of CAM cells connected to the match line. Therefore, detection of potential on the match line permits detecting the number of mismatched CAM cells.

摘要翻译： 每个匹配线连接到构成CAM阵列的多个CAM单元。 当通过字线选择时，相应的CAM单元存储在其数据存储部分中通过位线和反相位线施加的数据。 将存储的数据应用于数据比较部分，以与通过位线和反向位线施加的检索数据进行比较，从而检测它们之间的匹配或失配。 数据比较部分的比较结果首先以电荷的形式存储在电容元件中。 为了防止存储在电容元件中的信息的逸出，阻塞装置阻挡电容元件的充电和放电路径的一部分。 当在电容元件中存储不匹配的信息时，设置在电容元件和匹配线之间的电荷转移装置将一定量的电荷从两者之一传递到另一个。 这导致匹配线上的电荷电位波动。 匹配线上的电位波动取决于连接到匹配线的多个CAM单元中不匹配的CAM单元的数量。 因此，匹配线上的电位检测允许检测不匹配的CAM单元的数量。

公开(公告)号：US4965767A

公开(公告)日：1990-10-23

申请号：US380428

申请日：1989-07-17

申请人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

发明人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

IPC分类号： G11C15/04

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.

摘要翻译： 公开了仅由四个NMOS晶体管组成的相关存储器的存储单元电路。 电路的每个存储单元连接两个位线，字线，用于命令一致检测的匹配设置线和用于传送检测结果的匹配线。 数据信号以每个晶体管3的栅极容量存储。这种简化的存储单元电路有助于关联存储器的更高的集成。

公开(公告)号：US5126968A

公开(公告)日：1992-06-30

申请号：US605707

申请日：1990-10-30

申请人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Toshifumi Kobayashi ,  Tadato Yamagata ,  Masaaki Mihara

IPC分类号： G11C15/04

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of "1" is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data "1", writing of the data "1" onto the bit lines and the inversion bit lines is performed. Then, the data of "0" is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data "0", writing of the data "0" onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.

摘要翻译： 半导体存储器件包括多个或多个单元。 在刷新操作中，将数据“1”应用于所有位线和反转位线。 在存储数据“1”的CAM单元中，执行数据“1”到位线和反转位线的写入。 然后，将数据“0”应用于所有的位线和反转位线。 在存储数据“0”的CAM单元中，执行数据“0”到位线和反转位线的写入。 在部分写入操作中，在执行写入的CAM单元中，第一控制节点被激活，从而使得可以写入CAM单元。 在其余的CAM单元中，第一控制节点被去激活，从而不可能写入CAM单元。

公开(公告)号：US5418923A

公开(公告)日：1995-05-23

申请号：US937763

申请日：1992-09-01

申请人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

发明人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： An encoding circuit shortens time required for a coincidence signal to be converted into an address code after selected and output sequentially according to a predetermined priority level when the coincidence signal is obtained from an associative memory. The circuit is provided with a contention arbitrating circuit for a lower subgroup and a contention arbitrating circuit for a higher subgroup. In the contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for higher subgroup, each coincidence signal simultaneously activates inhibiting signals whose priority levels are lower than the priority level of the coincidence signal. A lower half of coincidence signals are arranged in descending order in the contention arbitrating circuit for a lower subgroup and a higher half of coincidence signals are arranged in ascending order in the contention arbitrating circuit for a higher subgroup. The contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for a higher subgroup are arranged in a triangular array and a complementary triangular array, respectively.

摘要翻译： 当从联想存储器获得符合信号时，编码电路将一致信号所需的时间缩短为根据预定的优先级依次选择和输出之后被转换成地址码。 该电路设置有用于较低子组的竞争仲裁电路和用于较高子组的争用仲裁电路。 在用于较低子组的竞争仲裁电路和较高子组的竞争仲裁电路中，每个符合信号同时激活优先级低于一致信号的优先级的禁止信号。 在下一个子组的竞争仲裁电路中，按照降序排列下半部分的符合信号，并且在较高子组的竞争仲裁电路中按照升序排列较高的一半符号信号。 用于较低子组的争用仲裁电路和用于较高子组的争用仲裁电路分别以三角阵列和互补三角阵列排列。

公开(公告)号：US5388066A

公开(公告)日：1995-02-07

申请号：US084098

申请日：1993-07-01

申请人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

IPC分类号： G06F17/30 ,  G11C15/00 ,  G11C15/04

CPC分类号： G06F17/30982 ,  G11C15/00 ,  G11C15/04 ,  G11C15/043

摘要： A data storing circuit including memory cells arranged in a plurality of rows and columns and flag cells corresponding to respective rows for storing flag information, the memory cells and the flag cell of the same row constituting one word, is provided. When a retrieval data is externally applied, the data included in the retrieval data is compared with the data of the memory cell, and the flag information stored in the retrieval data is compared with the flag stored in the flag cell. Respective results of comparison are output to a match line. Logical operation circuit carries out logical operation dependent on the result of comparison output to the match line, and writes the logical output to the flag cell of the data storing circuit.

摘要翻译： 一种数据存储电路，其特征在于，具备排列成多个行和列的存储单元以及对应于各行的标志单元，用于存储标志信息，存储单元和构成一个字的同一行的标志单元。 当外部应用检索数据时，将包括在检索数据中的数据与存储单元的数据进行比较，并将存储在检索数据中的标志信息与存储在标志单元中的标志进行比较。 比较结果输出到匹配行。 逻辑运算电路根据比较结果输出到匹配线进行逻辑运算，并将逻辑输出写入数据存储电路的标志单元。

公开(公告)号：US5319589A

公开(公告)日：1994-06-07

申请号：US966921

申请日：1992-10-27

申请人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

发明人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

IPC分类号： G11C15/00 ,  G11C11/4094 ,  G11C15/04 ,  G11C29/04

CPC分类号： G11C11/4094 ,  G11C15/043

摘要： A bit line control circuit is disclosed for implementing a dynamic content addressable memory. The bit line control circuit includes a read circuit 12 and a first write circuit 13 connected to data line pairs DT, /DT, a sense amplifier 14, a bit line discharge circuit 15, a bit line charge circuit 16, a transfer gate circuit 17, and a second write circuit 18. The bit line control circuit is connected to a CAM cell array through bit lines BLa, /BLa. Various operations such as write, read, refresh and match detection and the like necessary in the dynamic associative memory can be implemented under simple timing control by a simple circuit configuration.

摘要翻译： 公开了一种用于实现动态内容可寻址存储器的位线控制电路。 位线控制电路包括读取电路12和连接到数据线对DT，/ DT的第一写入电路13，读出放大器14，位线放电电路15，位线充电电路16，传输门电路17 和第二写入电路18.位线控制电路通过位线BLa，/ BLa连接到CAM单元阵列。 可以通过简单的电路配置在简单的定时控制下，在动态关联存储器中所需的诸如写入，读取，刷新和匹配检测等各种操作。

公开(公告)号：US4924220A

公开(公告)日：1990-05-08

申请号：US286922

申请日：1988-11-18

申请人： Masaaki Mihara ,  Toshifumi Kobayashi

发明人： Masaaki Mihara ,  Toshifumi Kobayashi

IPC分类号： G06F15/16 ,  G06F13/14 ,  G06F13/362 ,  G06F13/364 ,  G06F15/177

CPC分类号： G06F13/14 ,  G06F13/364

摘要： An arbiter circuit is disclosed for processing competing requests for access to a shared resource made simultaneously by two subsystems in a multi-processor system. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates, and functions to block the passage of a subsequent request signal from one subsystem to the SR flip-flop during a predetermined time interval after a request signal from the other subsystem has been supplied to the flip-flop. A result is that the both inputs of the SR flip-flop are not shifted up from the low levels to the high levels at the same time by the simultaneous generation of request signals from both subsystems, thereby eliminating any possibility of the output from the flip-flop floating at an intermediate level between the high and low level.

摘要翻译： 公开了一种仲裁器电路，用于处理在多处理器系统中由两个子系统同时进行的对共享资源的访问的竞争请求。 仲裁器电路包括由一对NAND门组成的SR触发器，并且在来自另一个子系统的请求信号之后的预定时间间隔期间阻止后续请求信号从一个子系统到SR触发器的通过 已被提供给触发器。 结果是，通过同时生成来自两个子系统的请求信号，SR触发器的两个输入都不会从低电平向上移动到高电平，从而消除了从翻转的输出的任何可能性 - 浮动在高低位之间的中间水平。

公开(公告)号：US4998027A

公开(公告)日：1991-03-05

申请号：US491014

申请日：1990-03-09

申请人： Masaaki Mihara ,  Toshifumi Kobayashi

发明人： Masaaki Mihara ,  Toshifumi Kobayashi

IPC分类号： G06F13/362 ,  G06F13/364 ,  H03K17/00

CPC分类号： G06F13/364

摘要： Disclosed is an arbiter circuit for arbitrating a contention between two request signals which simultaneously attain the H (logical high) level indicating a "request". In this arbiter circuit, buffer circuits, having different input logic threshold voltages, are connected to the respective outputs of two three-input NAND gates. The respective outputs of these two buffer circuits, as signals indicating "acknowledgement" or "negative acknowledgement" of the request signals, are derived as final outputs of the arbiter circuit. One of the buffer circuits has an input logic threshold voltage lower than a logic threshold voltage of the two NAND gates, while the other buffer circuit has an input logic threshold voltage set higher than the logic threshold voltage of the NAND gates. Therefore, when the NAND gates output a voltage with the logic level neither the H level nor the L (logical low) level, a signal of the logic level H indicating the "negative acknowledgement" and a signal of the logical level L indicating the "acknowledgement" are reliably outputted from the buffer circuit with the lower input logic threshold voltage and from the other buffer circuit with the higher input logic threshold voltage, respectively. That is, even if two requests occur simultaneously, one of the request signals is rapidly acknowledged.

摘要翻译： 公开了一种用于仲裁同时达到表示“请求”的H（逻辑高）电平的两个请求信号之间的争用的仲裁电路。 在该仲裁器电路中，具有不同输入逻辑阈值电压的缓冲电路连接到两个三输入NAND门的相应输出。 这两个缓冲电路的各自的输出，作为指示请求信号的“确认”或“否定确认”的信号被导出为仲裁器电路的最终输出。 其中一个缓冲电路具有低于两个NAND门的逻辑阈值电压的输入逻辑阈值电压，而另一个缓冲电路的输入逻辑阈值电压设置为高于NAND门的逻辑门限电压。 因此，当NAND门不产生具有H电平和L（逻辑低）电平的逻辑电平的电压时，指示“否定确认”的逻辑电平H的信号和表示“ 确认“能够从具有较低输入逻辑阈值电压的缓冲电路和具有较高输入逻辑阈值电压的另一缓冲电路可靠地输出。 也就是说，即使两个请求同时发生，一个请求信号被快速确认。

公开(公告)号：US08017994B2

公开(公告)日：2011-09-13

申请号：US12499220

申请日：2009-07-08

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

IPC分类号： H01L29/792

CPC分类号： G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568

摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。