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    READ CHANNEL DATA SIGNAL DETECTION WITH REDUCED-STATE TRELLIS
    111.
    发明申请
    READ CHANNEL DATA SIGNAL DETECTION WITH REDUCED-STATE TRELLIS 审中-公开
    阅读频道数据信号检测与减少状态TRELLIS

    公开(公告)号：US20140181625A1

    公开(公告)日：2014-06-26

    申请号：US13721417

    申请日：2012-12-20

    Applicant: LSI CORPORATION

    Inventor： Weijun Tan ,  Xuebin Wu ,  Shaohua Yang

    IPC: H03M13/25

    CPC classification number: H03M13/3746 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/29 ,  H03M13/6331

    Abstract: An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to determine a first set of soft outputs, hard decisions and reliability indicators for a read channel data signal, to determine a second set of soft outputs, hard decisions and reliability indicators based at least in part on the first set of soft outputs, hard decisions and reliability indicators, and to perform an iterative decoding process to decode the read channel data signal based at least in part on the second set of soft outputs, hard decisions and reliability indicators. The first set of soft outputs, hard decisions and reliability indicators are used to determine a reduced-state trellis for determining the second set of soft outputs, hard decisions and reliability indicators.

    Abstract translation: 一种装置包括读通道电路和与读通道电路相关联的信号处理电路。 信号处理电路被配置为确定用于读通道数据信号的第一组软输出，硬判决和可靠性指示符，以至少部分地基于第一组来确定第二组软输出，硬判决和可靠性指示符 软输出，硬判决和可靠性指示器，并且执行迭代解码处理，以至少部分地基于第二组软输出，硬判决和可靠性指示器来解码读通道数据信号。 第一组软输出，硬判决和可靠性指标用于确定用于确定第二组软输出，硬判决和可靠性指标的缩小状态网格。

    Low Density Parity Check Decoder With Dynamic Scaling
    113.
    发明申请
    Low Density Parity Check Decoder With Dynamic Scaling 有权
    低密度奇偶校验解码器与动态缩放

    公开(公告)号：US20140173385A1

    公开(公告)日：2014-06-19

    申请号：US13777841

    申请日：2013-02-26

    Applicant: LSI CORPORATION

    Inventor： Shu Li ,  Zongwang Li ,  Shaohua Yang ,  Chung-Li Wang ,  Fan Zhang

    IPC: H03M13/13 ,  G11B20/18

    CPC classification number: H03M13/1117 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1111 ,  H03M13/1171 ,  H03M13/27 ,  H03M13/6331 ,  H03M13/658

    Abstract: A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

    Abstract translation: 公开了一种数据处理系统，包括具有可变节点处理器的低密度奇偶校验解码器，校验节点处理器和缩放器电路。 低密度奇偶校验解码器可用于在缩放器电路中缩放具有缩放因子的软信息，同时在可变节点处理器和变量节点中对可变节点消息进行迭代生成并处理校验节点，以校验校验节点处理器中的节点消息 多个检查节点和可变节点。 缩放因子是从低密度奇偶校验解码器的输入中的可能值的分布导出的。

    Read channel error correction using multiple calibrators
    114.
    发明授权
    Read channel error correction using multiple calibrators 有权
    使用多个校准器读取通道错误校正

    公开(公告)号：US08730606B1

    公开(公告)日：2014-05-20

    申请号：US13681917

    申请日：2012-11-20

    Applicant: LSI Corporation

    Inventor： Weijun Tan ,  Shaohua Yang

    IPC: G11B5/09

    CPC classification number: G11B20/18 ,  G11B20/10046 ,  G11B20/1816 ,  G11B20/1833 ,  G11B2020/185

    Abstract: Read channel circuitry comprises a decoder and error correction circuitry. The error correction circuitry is configured to calibrate a first set of filters using a read channel data signal, to determine first hard decision information regarding the read channel data signal using the calibrated first set of filters, to determine an error corrected read channel data signal using the first hard decision information, to calibrate a second set of filters using the error corrected read channel data signal, to determine second hard decision information regarding the error corrected read channel data signal using the calibrated second set of filters, and to decode the second hard decision information. The first set of filters and the second set of filters are calibrated in respective first and second calibrators.

    Abstract translation: 读通道电路包括解码器和纠错电路。 误差校正电路被配置为使用读取通道数据信号来校准第一组滤波器，以使用校准的第一组滤波器来确定关于读取的通道数据信号的第一硬判决信息，以使用以下方式确定纠错的读通道数据信号： 第一硬判决信息，使用纠错的读通道数据信号来校准第二组滤波器，以使用校准的第二组滤波器来确定关于纠错的读通道数据信号的第二硬判决信息，并且解码第二硬 决策信息。 第一组滤波器和第二组滤波器在相应的第一和第二校准器中校准。

    MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE FOR MAGNETIC RECORDING CHANNEL
    116.
    发明申请
    MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE FOR MAGNETIC RECORDING CHANNEL 有权
    多级运行有限公司有限公司磁记录通道有限公司

    公开(公告)号：US20140111880A1

    公开(公告)日：2014-04-24

    申请号：US13654893

    申请日：2012-10-18

    Applicant: LSI CORPORATION

    Inventor： Wu Chang ,  Razmik Karabed ,  Shaohua Yang ,  Fan Zhang

    IPC: G11B5/02

    CPC classification number: G11B5/02 ,  G06F11/16 ,  G11B20/10277

    Abstract: A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure.

    Abstract translation: 描述了一种基于多级游程限制有限状态机来构建最大过渡运行调制码的系统。 处理器被配置为经由读取通道从硬盘驱动器接收信息，并使用最大过渡运行调制码从硬盘驱动器恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化马尔可夫源，并且构建最大过渡运行调制码 基于具有有限转换行程长度和多级周期性结构的有限状态机模拟优化的马尔可夫源。

    Systems and methods for sync mark mis-detection protection
    118.
    发明授权
    Systems and methods for sync mark mis-detection protection 有权
    用于同步标记错误检测保护的系统和方法

    公开(公告)号：US09424876B2

    公开(公告)日：2016-08-23

    申请号：US13896048

    申请日：2013-05-16

    Applicant: LSI Corporation

    Inventor： Shaohua Yang

    IPC: H04L7/00 ,  G11B20/10 ,  G11B20/18 ,  G06F11/263

    CPC classification number: G11B20/10305 ,  G06F11/263 ,  G11B20/10361 ,  G11B20/1037 ,  G11B20/1816

    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream. As an example, a data processing system is discussed that includes a sync mark detection circuit and a sync quality output circuit. The sync mark detection circuit is operable to identify a predefined pattern in a received data set, where identification of the predefined pattern results is asserting a sync found output, and where a preamble pattern precedes the predefined pattern in the received data set. The sync quality output circuit is operable to provide a sync mark quality metric indicating a similarity between the preamble pattern and the received data set within a region preceding the predefined pattern.

    Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于检测数据流中的模式的系统和方法。 作为示例，讨论了包括同步标记检测电路和同步质量输出电路的数据处理系统。 同步标记检测电路可操作以识别接收数据集中的预定义模式，其中预定义模式结果的识别确定发现同步发现输出，并且其中前导码模式在接收数据集中的预定模式之前。 同步质量输出电路可操作以提供指示在预定义模式之前的区域内的前导码模式和接收数据集之间的相似性的同步标记质量度量。

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