公开(公告)号：US07428649B2

公开(公告)日：2008-09-23

申请号：US10620470

申请日：2003-07-15

申请人： Lawrence T. Clark

发明人： Lawrence T. Clark

IPC分类号： G06F1/26

CPC分类号： H04B1/1615 ,  H04W52/028 ,  Y02D70/40

摘要： Circuitry gates the power supply to limit standby power in an integrated circuit. The IR drop through clamps may be compensated using a regulator feedback signal to improve the power performance and allow the power supply regulator to supply the best quality power signals possible.

摘要翻译： 电路对电源供电以限制集成电路中的待机功率。 通过钳位的IR降压可以使用调节器反馈信号进行补偿，以提高功率性能，并允许电源调节器提供最佳质量的功率信号。

公开(公告)号：US06775180B2

公开(公告)日：2004-08-10

申请号：US10329124

申请日：2002-12-23

申请人： Manish Biyani ,  Lawrence T. Clark ,  Shay P. Demmons ,  Franco Ricci

发明人： Manish Biyani ,  Lawrence T. Clark ,  Shay P. Demmons ,  Franco Ricci

IPC分类号： G11C1100

CPC分类号： G11C5/145

摘要： An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.

摘要翻译： 一种具有状态保持存储器结构以存储状态值的集成电路。 高性能部分使用薄栅氧化物晶体管，并且状态保持存储器结构使用厚栅极氧化物晶体管来捕获并保持在低功率模式下工作时的状态值。

公开(公告)号：US06774696B2

公开(公告)日：2004-08-10

申请号：US10318689

申请日：2002-12-12

申请人： Lawrence T. Clark ,  Shay P. Demmons ,  Franco Ricci ,  Tim Beatty

发明人： Lawrence T. Clark ,  Shay P. Demmons ,  Franco Ricci ,  Tim Beatty

IPC分类号： H03L500

CPC分类号： H03K3/356156

摘要： A level translator block receives a control signal and a data signal and provides an interface between circuitry operating in a first voltage domain and circuitry operating in a second voltage domain. Thick-oxide transistors are appropriately used in the level translator block to reduce gate leakage currents when translating signals.

摘要翻译： 电平转换器块接收控制信号和数据信号，并提供在第一电压域中操作的电路和在第二电压域中工作的电路之间的接口。 在电平转换器块中适当地使用厚氧化物晶体管，以在转换信号时减少栅极漏电流。

公开(公告)号：US06650589B2

公开(公告)日：2003-11-18

申请号：US09997809

申请日：2001-11-29

申请人： Lawrence T. Clark

发明人： Lawrence T. Clark

IPC分类号： G11C700

CPC分类号： G11C7/02 ,  G11C5/147 ,  G11C11/413 ,  G11C11/419

摘要： An integrated circuit having a microprocessor core and a memory block that may operate at different voltages. A voltage regulator, either external to the integrated circuit or designed as part of the integrated circuit, generates the two voltages. The operating voltage for the microprocessor core is selected to satisfy power and performance criteria while the operating voltage for the memory block is set to provide acceptable noise margins and maintain stability of the memory cells within the memory block.

公开(公告)号：US06549037B1

公开(公告)日：2003-04-15

申请号：US09602667

申请日：2000-06-26

申请人： Lawrence T. Clark ,  Kimberley E. Wagner

发明人： Lawrence T. Clark ,  Kimberley E. Wagner

IPC分类号： H03K190175

CPC分类号： H03K19/0016

摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit comprises a first stage that provides differential outputs in one mode and substantially equal outputs in another mode.

摘要翻译： 简而言之，根据本发明的一个实施例，集成电路包括第一级，其在一个模式中提供差分输出，并且在另一模式下基本相等的输出。

公开(公告)号：US06433822B1

公开(公告)日：2002-08-13

申请号：US09052749

申请日：1998-03-31

申请人： Lawrence T. Clark ,  Mark A. Beiley ,  Eric J. Hoffman

发明人： Lawrence T. Clark ,  Mark A. Beiley ,  Eric J. Hoffman

IPC分类号： H04N5217

CPC分类号： H04N5/361 ,  H04N5/2176 ,  H04N5/3658 ,  H04N5/378 ,  H04N17/002

摘要： An architecture for self-calibration and fixed-pattern noise removal in imager chips. The column-to-column fixed pattern noise and/or pixel-to-pixel fixed pattern noise is determined through a self-calibration operation. During operation of the imager chip, when a value of a pixel is read, the read value is compensated with the fixed-pattern noise corresponding to either the column fixed pattern noise corresponding to the column having the pixel from which the value was read or to the pixel fixed pattern noise corresponding to the pixel from which the value was read.

摘要翻译： 在成像器芯片中进行自校准和固定图案噪声去除的架构。 通过自校准操作来确定柱对列固定图案噪声和/或像素到像素的固定图案噪声。 在成像器芯片的操作期间，当读取像素的值时，读取值被对应于与具有读取该值的像素的列相对应的列固定图案噪声的固定图案噪声补偿，或者 对应于读取该值的像素的像素固定模式噪声。

公开(公告)号：US06426550B2

公开(公告)日：2002-07-30

申请号：US09805862

申请日：2001-03-14

申请人： Zane A. Ball ,  Aviram Gutman ,  Lawrence T. Clark

发明人： Zane A. Ball ,  Aviram Gutman ,  Lawrence T. Clark

IPC分类号： H01L2312

CPC分类号： H01L23/49822 ,  H01L2224/16225 ,  H05K1/0219 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09672

摘要： A multi-layer electronic device package includes first and second outer layers and at least one signal layer disposed between the outer layers. The signal layer includes signal traces and ground traces interleaved with the signal traces. A method of routing signal traces in an electronic device package includes the acts of disposing a plurality of signal traces in at least one substrate layer, and interleaving a plurality of ground traces with the signal traces.

公开(公告)号：US06425086B1

公开(公告)日：2002-07-23

申请号：US09302560

申请日：1999-04-30

申请人： Lawrence T. Clark ,  Bart McDaniel ,  Jay Heeb ,  Tom J. Adelmeyer

发明人： Lawrence T. Clark ,  Bart McDaniel ,  Jay Heeb ,  Tom J. Adelmeyer

IPC分类号： G06F132

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

摘要翻译： 简而言之，根据本发明的一个实施例，系统包括：处理器，电压调节器和存储器。 电压调节器耦合到处理器以调整处理器的工作电压。 存储器通过存储器总线耦合到处理器。 存储器已经存储有处理器指令，当处理器执行时，该指令导致处理器的工作频率的修改并且导致处理器的工作电压的调整，至少部分地基于处理器的动态变化 处理器的处理负载。

公开(公告)号：US06388315B1

公开(公告)日：2002-05-14

申请号：US09941829

申请日：2001-08-29

申请人： Lawrence T. Clark ,  Vikas R. Amrelia ,  Raphael A. Soetan ,  Eric J. Hoffman ,  Tuan X. Do

发明人： Lawrence T. Clark ,  Vikas R. Amrelia ,  Raphael A. Soetan ,  Eric J. Hoffman ,  Tuan X. Do

IPC分类号： H01L2352

CPC分类号： H01L23/5286 ,  H01L27/0203 ,  H01L27/118 ,  H01L2924/0002 ,  Y10T307/582 ,  H01L2924/00

摘要： An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

公开(公告)号：US06235549B1

公开(公告)日：2001-05-22

申请号：US09524081

申请日：2000-03-13

申请人： Edward J. Bawolek ,  Lawrence T. Clark ,  Mark A. Beiley

发明人： Edward J. Bawolek ,  Lawrence T. Clark ,  Mark A. Beiley

IPC分类号： H01L2100

CPC分类号： H01L27/14636 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14645 ,  H01L27/14654 ,  H01L27/14685 ,  H01L27/1469

摘要： A method and apparatus for employing a light shield to modulate pixel color responsivity. The improved pixel includes a substrate having a photodiode with a light receiving area. A color filter array material of a first color is disposed above the substrate. The pixel has a first relative responsivity. A light shield is disposed above the substrate to modulate the pixel color responsivity. The light shield forms an aperture whose area is substantially equal to the light receiving area adjusted by a reduction factor. The reduction factor is the result of an arithmetic operation between the first relative responsivity and a second relative responsivity, associated with a second pixel of a second color.

摘要翻译： 一种采用遮光罩来调制像素颜色响应度的方法和装置。 改进的像素包括具有光接收面积的光电二极管的基板。 第一颜色的滤色器阵列材料设置在基板上方。 像素具有第一相对响应度。 遮光板设置在基板上方以调制像素颜色响应度。 遮光板形成其面积基本上等于由减小因子调节的光接收面积的孔径。 缩小因子是与第二颜色的第二像素相关联的第一相对响应度和第二相对响应度之间的算术运算的结果。