公开(公告)号：US12067290B2

公开(公告)日：2024-08-20

申请号：US17591406

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Jung Sheng Hoei ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick R. Khayat

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

公开(公告)号：US20240134571A1

公开(公告)日：2024-04-25

申请号：US18401251

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sivagnanam Parthasarathy ,  Patrick R. Khayat ,  Sundararajan Sankaranarayanan ,  Jeremy Binfet ,  Akira Goda

IPC: G06F3/06 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G11C16/26 ,  G11C16/0483

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.

公开(公告)号：US20240071435A1

公开(公告)日：2024-02-29

申请号：US18198623

申请日：2023-05-17

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  Patrick R. Khayat ,  Jeffrey S. McNeil ,  Dung Viet Nguyen ,  Kishore Kumar Muchherla ,  James Fitzpatrick

IPC: G11C7/10

CPC classification number: G11C7/1069 ,  G11C7/1057 ,  G11C7/106

Abstract: Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.

公开(公告)号：US20240054046A1

公开(公告)日：2024-02-15

申请号：US17884076

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Vamsi Pavan Rayaprolu

IPC: G06F11/10 ,  G11C29/08

CPC classification number: G06F11/1044 ,  G11C29/08

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; responsive to determining that a data integrity metric value satisfies the threshold criterion, performing a first error-handling operation on the data stored on the source set of memory cells; responsive to determining that the first error-handling operation fails to correct the data, performing a second error-handling operation on the data; and responsive to determining that the second error-handling operation corrected the data, causing the memory device to copy the corrected data to a destination set of memory cells of the memory device.

公开(公告)号：US20240036973A1

公开(公告)日：2024-02-01

申请号：US17877637

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Dung Viet Nguyen ,  Zixiang Loh ,  Sampath K. Ratnam ,  Patrick R. Khayat ,  Thomas Herbert Lentz

IPC: G06F11/10

CPC classification number: G06F11/1044

Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.

公开(公告)号：US11854649B2

公开(公告)日：2023-12-26

申请号：US17675592

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Steven Michael Kientz ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu

IPC: G11C7/04 ,  G11C16/08 ,  G11C16/26 ,  G06F3/06

CPC classification number: G11C7/04 ,  G06F3/064 ,  G11C16/08 ,  G11C16/26

Abstract: A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

公开(公告)号：US20230395161A1

公开(公告)日：2023-12-07

申请号：US17860690

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Patrick R. Khayat ,  Sivagnanam Parthasarathy

IPC: G11C16/26 ,  G11C16/34 ,  G06F3/06

CPC classification number: G11C16/26 ,  G11C16/3459 ,  G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/0483

Abstract: Embodiments disclosed can include selecting a target read window budget (RWB) increase and identifying a set of aggressor memory cells. They can also include generating a list of programming level states for the set of aggressor memory cells and identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to the target RWB increase. They can further include responsive to identifying the entry with the total number of bits associated with a maximum RWB increase that is greater than or equal to the target RWB increase, modifying a parameter of the memory access operation with the adjustment associated with the identified entry.

公开(公告)号：US20230359388A1

公开(公告)日：2023-11-09

申请号：US17735458

申请日：2022-05-03

Applicant: Micron Technology, Inc.

Inventor： Dung Viet Nguyen ,  Patrick R. Khayat ,  Zhengang Chen ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metadata characterizing voltage distributions. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: receiving one or more metadata values characterizing threshold voltage distributions of a subset of the plurality of memory cells connected to one or more bitlines, wherein the one or more metadata values reflect a conductive state of the one or more bitlines; determining a read voltage adjustment value based on the one or more metadata values; and applying the read voltage adjustment value for reading the subset of the plurality of memory cells.

公开(公告)号：US20230266901A1

公开(公告)日：2023-08-24

申请号：US17675624

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Patrick R. Khayat ,  Steven Michael Kientz ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0625 ,  G06F3/0679

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

公开(公告)号：US20220091935A1

公开(公告)日：2022-03-24

申请号：US17544772

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Larry J. Koudele ,  Michael Sheperek ,  Patrick R. Khayat ,  Sampath K. Ratnam

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.