公开(公告)号：US11581317B2

公开(公告)日：2023-02-14

申请号：US17362790

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Srinivas Pulugurtha ,  Richard J. Hill ,  Yunfei Gao ,  Nicholas R. Tapias ,  Litao Yang ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230033803A1

公开(公告)日：2023-02-02

申请号：US17443531

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Harsh Narendrakumar Jain ,  Naveen Kaushik ,  Adam L. Olson ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

公开(公告)号：US20230032177A1

公开(公告)日：2023-02-02

申请号：US17443521

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain ,  Adam L. Olson ,  Yoshiaki Fukuzumi ,  Naveen Kaushik ,  Richard J. Hill ,  Lars P. Heineck

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  H01L23/00

Abstract: An electronic device comprising multilevel bitlines, pillar contacts, level 1 contacts, and level 2 contacts. The multilevel bitlines comprise first bitlines and second bitlines, with the first bitlines and second bitlines positioned at different levels. The pillar contacts are electrically connected to the first bitlines and to the second bitlines, the level 1 contacts are electrically connected to the first bitlines, and the level 2 contacts are electrically connected to the second bitlines. Each bitline of the first bitlines is electrically connected to a single pillar contact adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20220310831A1

公开(公告)日：2022-09-29

申请号：US17840250

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  John F. Kaeding ,  Richard J. Hill ,  Scott E. Sills

IPC: H01L29/76 ,  H01L29/66 ,  H01L27/11509 ,  H01L27/108 ,  H01L29/16 ,  H01L29/26 ,  H01L29/786 ,  H01L21/02 ,  H01L27/11507

Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220069133A1

公开(公告)日：2022-03-03

申请号：US17005054

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： David K. Hwang ,  Richard J. Hill ,  Gurtej S. Sandhu

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12

Abstract: Some embodiments include an integrated assembly having an upwardly-extending structure with a sidewall surface. Two-dimensional-material extends along the sidewall surface. First electrostatic-doping-material is adjacent a lower region of the two-dimensional-material, insulative material is adjacent a central region of the two-dimensional-material, and second electrostatic-doping-material is adjacent an upper region of the two-dimensional-material. A conductive-gate-structure is over the first electrostatic-doping-material and adjacent to the insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220068955A1

公开(公告)日：2022-03-03

申请号：US17007951

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L27/11582 ,  H01L21/762 ,  H01L29/06

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US11189629B2

公开(公告)日：2021-11-30

申请号：US16863120

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies.

公开(公告)号：US20210335817A1

公开(公告)日：2021-10-28

申请号：US17369605

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20210327883A1

公开(公告)日：2021-10-21

申请号：US17362790

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Srinivas Pulugurtha ,  Richard J. Hill ,  Yunfei Gao ,  Nicholas R. Tapias ,  Litao Yang ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11107830B2

公开(公告)日：2021-08-31

申请号：US16548267

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  H01L29/792

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.