公开(公告)号：US20200143872A1

公开(公告)日：2020-05-07

申请号：US16734241

申请日：2020-01-03

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C11/406 ,  G11C11/16 ,  G11C13/00 ,  G11C11/22 ,  G11C11/00

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US20190325966A1

公开(公告)日：2019-10-24

申请号：US15959868

申请日：2018-04-23

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC: G11C16/14 ,  G11C16/08 ,  G11C17/16 ,  G11C17/18 ,  G11C16/22 ,  G11C13/00 ,  G11C11/16 ,  G11C11/22 ,  G11C16/30

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

公开(公告)号：US20190295666A1

公开(公告)日：2019-09-26

申请号：US15933678

申请日：2018-03-23

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  George B. Raad ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C16/34 ,  G11C11/406

Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

公开(公告)号：US20190228816A1

公开(公告)日：2019-07-25

申请号：US16375073

申请日：2019-04-04

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/005 ,  G11C11/1675 ,  G11C11/2275 ,  G11C13/0033 ,  G11C13/0069

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US10297309B1

公开(公告)日：2019-05-21

申请号：US16015441

申请日：2018-06-22

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C7/00 ,  G11C11/406

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US20140237305A1

公开(公告)日：2014-08-21

申请号：US13771838

申请日：2013-02-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： James S. Rehmeyer ,  John F. Schreck ,  Timothy B. Cowles

IPC: G06F11/07

CPC classification number: G11C29/40 ,  G01R31/31703 ,  G01R31/3187 ,  G01R31/3193 ,  G01R31/31932 ,  G01R31/31935 ,  G06F11/076 ,  G11C29/44 ,  G11C29/48 ,  G11C29/70 ,  G11C2029/4002 ,  G11C2029/5606

Abstract: Apparatuses and methods for compressing data responsive to a plurality of memory accesses is described. An example compression circuit includes a comparator configured to compare data provided by a group of memory cells associated with a repair address. Each subset of one or more bits of the data is sequentially provided by the group of memory cells responsive to a respective memory access of a plurality of memory accesses. The example compression circuit further including an error bit latch coupled to the comparison circuit. The error bit latch configured to, responsive to an output received from the comparison circuit indicating an error, compress the data to an error bit by setting the error bit to an error detected state and latching the error bit having the error detected state.

Abstract translation: 描述了响应于多个存储器访问来压缩数据的装置和方法。 示例压缩电路包括比较器，其被配置为比较由与修复地址相关联的一组存储器单元提供的数据。 响应于多个存储器访问的相应存储器访问，由该组存储器单元顺序地提供数据的一个或多个位的每个子集。 示例压缩电路还包括耦合到比较电路的错误位锁存器。 错误位锁存器被配置为响应于从比较电路接收的指示错误的输出，通过将错误位设置为错误检测状态并锁存具有错误检测状态的错误位来将数据压缩到错误位。

公开(公告)号：US20240320169A1

公开(公告)日：2024-09-26

申请号：US18731979

申请日：2024-06-03

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G06F13/16 ,  G11C17/14 ,  G11C17/18

CPC classification number: G06F13/1689 ,  G11C17/143 ,  G11C17/18

Abstract: A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.

公开(公告)号：US12001356B2

公开(公告)日：2024-06-04

申请号：US17463318

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G06F13/16 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18

CPC classification number: G06F13/1689 ,  G11C17/143 ,  G11C17/18

Abstract: A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.

公开(公告)号：US11954338B2

公开(公告)日：2024-04-09

申请号：US17544407

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt

IPC: G11C7/00 ,  G06F3/06 ,  G11C29/44

CPC classification number: G06F3/0626 ,  G06F3/0635 ,  G06F3/0679 ,  G11C29/44

Abstract: A memory device includes a memory cell array and a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array. The memory device including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells. Each match sub-circuit can be configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell. The plurality of match sub-circuit can include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information. The common bit-processing circuit can determine whether the common bit information matches the portion of the memory cell address.

公开(公告)号：US11948660B2

公开(公告)日：2024-04-02

申请号：US17381057

申请日：2021-07-20

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  Lawrence D. Smith ,  James S. Rehmeyer

IPC: G11C7/22 ,  G11C7/10 ,  G11C17/16

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/109 ,  G11C17/16

Abstract: Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.