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公开(公告)号：US20050234614A1
公开(公告)日：2005-10-20
申请号：US11053842
申请日：2005-02-10
CPC分类号： B62D5/049 , B62D5/0493
摘要： A vehicle controller which can realize a reduced cost and high reliability at the same time. A control target status signal outputted from a control target is inputted to a monitoring unit. The monitoring unit compares a control command value with the control target status signal to determine whether the control target operates normally as per the control command value. When the monitoring unit determines that the control target does not operate normally, it outputs a failure detected signal to an actuator driving unit.
摘要翻译： 一种能同时实现降低成本和高可靠性的车辆控制器。 从控制目标输出的控制目标状态信号被输入到监视单元。 监视单元将控制命令值与控制目标状态信号进行比较，以根据控制命令值来确定控制目标是否正常工作。 当监视单元确定控制目标不能正常工作时，它向致动器驱动单元输出故障检测信号。
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公开(公告)号：US20050172059A1
公开(公告)日：2005-08-04
申请号：US11016769
申请日：2004-12-21
CPC分类号： G06F13/4291 , G06F9/54 , G06F13/102 , H04L12/40019 , H04L12/403 , H04L2012/40273
摘要： A data communication system uses an SPI bus having a plurality of devices wherein data communications are enabled using communication protocols optimum to respective devices. The system includes a master device connected to a plurality of slave devices via a data transmission bus by which the master device transfers data to the slave devices, or a data reception bus by which the master device receives data from the slave devices, in a synchronism with a synchronous clock signal. Chip select signal lines also connect the master device to the slave devices, on a one to one basis. Communication drivers set a physical protocol of each slave device, and a communication manager arbitrates serial communications between the master device and the slave devices by their proper physical protocols. Communication protocols such as baud rates, clock polarities, and clock phases are switched by asserted Chip Select signal lines.
摘要翻译： 数据通信系统使用具有多个设备的SPI总线，其中使用对各个设备最佳的通信协议来启用数据通信。 该系统包括：主设备经由数据传输总线连接到多个从设备的主设备，主设备通过该数据传输总线将数据传输到从设备，或者主设备通过该数据接收总线以同步方式从从设备接收数据 具有同步时钟信号。 芯片选择信号线还将主器件一对一连接到从器件。 通信驱动器设置每个从设备的物理协议，并且通信管理器通过其适当的物理协议来仲裁主设备和从设备之间的串行通信。 诸如波特率，时钟极性和时钟相位之类的通信协议由断言的片选信号线切换。
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公开(公告)号：US06625522B2
公开(公告)日：2003-09-23
申请号：US09801656
申请日：2001-03-09
IPC分类号： G06F700
CPC分类号： B60W50/00 , B60T8/885 , B60T2270/406 , B60W50/0205 , B60W2050/0006 , F02D41/22 , F02D41/266 , F02D41/3005 , F02D2400/18
摘要： A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have an independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.
摘要翻译： 低成本车辆控制系统和使用该系统的汽车控制致动器驱动器的辐射，从而降低辐射部件成本，并允许电子控制单元的小型化以提高通用性。 车辆控制系统具有电子控制单元，用于在致动器侧驱动致动器的多个致动器和致动器驱动器。 执行器驱动器分别具有独立的自诊断部分，自保护部分和通信控制部分，并且相应地分散到致动器。
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公开(公告)号：US06624474B2
公开(公告)日：2003-09-23
申请号：US09943384
申请日：2001-08-31
IPC分类号： H01L2701
CPC分类号： H01L27/12 , H01L21/76229 , H01L21/84 , Y10T307/747
摘要： A semiconductor device comprises an embedded insulation layer 101 formed on a semiconductor substrate 100, plural power semiconductor elements 2, 3 formed on a semiconductor substrate 100 on the embedded insulation layer, a trench 4 formed on the semiconductor substrate and isolating between the power semiconductor elements, and an isolator 5 insulating and driving control electrodes of the power semiconductor elements, and the power semiconductor elements 2, 3 such as transistors can be used, being connected each other in series.
摘要翻译： 半导体器件包括形成在半导体衬底100上的嵌入绝缘层101，形成在嵌入绝缘层上的半导体衬底100上的多个功率半导体元件2,3，形成在半导体衬底上的沟槽4，并且在功率半导体元件 隔离器5可以使用功率半导体元件的绝缘和驱动控制电极以及诸如晶体管的功率半导体元件2,3串联连接。
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公开(公告)号：US06600295B2
公开(公告)日：2003-07-29
申请号：US09943386
申请日：2001-08-31
IPC分类号： G05F110
CPC分类号： H02M3/156
摘要： In order to ensures a stable reduction of noise level at all times, in the steps of switching input voltage with a switching element 10, smoothing the voltage of rectangular wave obtained by switching with a reactor L and capacitor Cf and outputting it, the voltage obtained by dividing the output voltage is compared with the sawtooth wave output from a sawtooth wave generator 14 by a comparator 12. When the switching signal in response to the result of this comparison is applied to the switching element 10, the counter 16 is actuated synchronously with the vertex of the sawtooth wave to perform opening/closing operation of the switch SW1. The time constant of the time constant circuit comprising a R0 and C is adjusted according to whether a resistor R1 is present or not, and the signals of frequencies f1 and f2 coming out of the sawtooth wave generator 14 are sequentially switched to be sent to the comparator 12. The peak of the switching noise is diffused in the frequency range by sequential selection of switching frequencies, and noise level is reduced by diffusion of noise energy.
摘要翻译： 为了始终确保噪声电平的稳定降低，在利用开关元件10切换输入电压的步骤中，平滑通过用电抗器L和电容器Cf切换而获得的矩形波的电压并输出，获得的电压 通过将输出电压除以与比较器12的锯齿波发生器14输出的锯齿波进行比较，当将与该比较结果对应的切换信号应用于开关元件10时，计数器16与 锯齿波的顶点来执行开关SW1的打开/关闭操作。 根据是否存在电阻R1来调整包括R0和C的时间常数电路的时间常数，并且顺序地切换从锯齿波发生器14出来的频率f1和f2的信号被发送到 比较器12.开关噪声的峰值通过顺序选择开关频率而在频率范围内扩散，噪声电平通过噪声能量的扩散而减小。
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公开(公告)号：US06584004B2
公开(公告)日：2003-06-24
申请号：US09793968
申请日：2001-02-28
申请人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
发明人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
IPC分类号： H01L2328
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
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117.发明授权Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them 失效信息处理系统和逻辑LSI，通过使用它们中的每一个处理的内部数据来检测系统或LSI中的故障公开(公告)号：US06385755B1
公开(公告)日：2002-05-07
申请号：US09613276
申请日：2000-07-10
IPC分类号： G11C2900
CPC分类号： G06F11/1637 , G06F11/1654 , G06F11/2025 , G06F11/2038 , G06F11/2043
摘要： An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.
摘要翻译： 信息处理系统具有多个处理器电路，每个处理器电路包括内部电路和内部处理结果输出电路，该系统具有连接到每个处理器电路的内部数据选择电路和至少一个故障检测电路。 每个处理器电路的内部处理结果输出电路输出由处理器电路中的各个内部电路处理的各个结果数据。 每个内部数据选择电路在预定的定时选择并输出从每个处理器电路的内部处理结果输出电路输出的一个选择的结果数据。 故障检测电路输出由处理器电路的各个内部数据选择电路选择的数据或由处理器电路在每个预定定时输出的数据之间的比较结果。
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公开(公告)号：US5084878A
公开(公告)日：1992-01-28
申请号：US420473
申请日：1989-10-12
IPC分类号： G06F11/18
CPC分类号： G06F11/187
摘要： Input signals supplied to a plurality redundant subsystems are input to an output selecting circuit after an output of a subsystem is changed from an output signal of a subsystem having a most reliable output signal to another output signal of another subsystem having a lower reliable output signal in turn using self-diagnoses and cross-diagnoses in each subsystem according to an algorithm as follows:if any subsystem has Syndrome 1 then select the subsystem(s) which has Syndrome 1,else if any subsystem has Syndrome 2 then select the subsystem(s) which has Syndrome 2;else if any subsystem has Syndrome L-1 then select the subsystem(s) which has Syndrome L-1;else output fail safe signal.The output selecting circuit outputs a selected signal by a method of majority voting based on the output signals from the subsystems.
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